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/kernel/linux/linux-5.10/drivers/net/dsa/
Dmv88e6060.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * drivers/net/dsa/mv88e6060.h - Marvell 88e6060 switch chip support
17 #define PORT_STATUS_PAUSE_EN BIT(15)
18 #define PORT_STATUS_MY_PAUSE BIT(14)
20 #define PORT_STATUS_RESOLVED BIT(13)
21 #define PORT_STATUS_LINK BIT(12)
22 #define PORT_STATUS_PORTMODE BIT(11)
23 #define PORT_STATUS_PHYMODE BIT(10)
24 #define PORT_STATUS_DUPLEX BIT(9)
25 #define PORT_STATUS_SPEED BIT(8)
[all …]
/kernel/linux/linux-4.19/drivers/net/dsa/
Dmv88e6060.h2 * drivers/net/dsa/mv88e6060.h - Marvell 88e6060 switch chip support
21 #define PORT_STATUS_PAUSE_EN BIT(15)
22 #define PORT_STATUS_MY_PAUSE BIT(14)
24 #define PORT_STATUS_RESOLVED BIT(13)
25 #define PORT_STATUS_LINK BIT(12)
26 #define PORT_STATUS_PORTMODE BIT(11)
27 #define PORT_STATUS_PHYMODE BIT(10)
28 #define PORT_STATUS_DUPLEX BIT(9)
29 #define PORT_STATUS_SPEED BIT(8)
36 #define PORT_CONTROL_FORCE_FLOW_CTRL BIT(15)
[all …]
/kernel/linux/linux-5.10/include/soc/mscc/
Docelot_dev.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
11 #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7)
12 #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6)
13 #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5)
14 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4)
15 #define DEV_CLOCK_CFG_PORT_RST BIT(3)
16 #define DEV_CLOCK_CFG_PHY_RST BIT(2)
20 #define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4)
21 #define DEV_PORT_MISC_FWD_PAUSE_ENA BIT(3)
22 #define DEV_PORT_MISC_FWD_CTRL_ENA BIT(2)
[all …]
Docelot_hsio.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
85 #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
86 #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
87 #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
88 #define HSIO_PLL5G_CFG0_DIV4 BIT(28)
89 #define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
99 #define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
100 #define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14)
101 #define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13)
102 #define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12)
[all …]
Docelot_ana.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
11 #define ANA_ANAGEFIL_B_DOM_EN BIT(22)
12 #define ANA_ANAGEFIL_B_DOM_VAL BIT(21)
13 #define ANA_ANAGEFIL_AGE_LOCKED BIT(20)
14 #define ANA_ANAGEFIL_PID_EN BIT(19)
18 #define ANA_ANAGEFIL_VID_EN BIT(13)
19 #define ANA_ANAGEFIL_VID_VAL(x) ((x) & GENMASK(12, 0))
20 #define ANA_ANAGEFIL_VID_VAL_M GENMASK(12, 0)
27 #define ANA_STORMLIMIT_CFG_STORM_UNIT BIT(2)
31 #define ANA_AUTOAGE_AGE_FAST BIT(21)
[all …]
/kernel/linux/linux-5.10/sound/firewire/bebob/
Dbebob_command.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * bebob_command.c - driver for BeBoB based devices
5 * Copyright (c) 2013-2014 Takashi Sakamoto
16 buf = kzalloc(12, GFP_KERNEL); in avc_audio_set_selector()
18 return -ENOMEM; in avc_audio_set_selector()
30 err = fcp_avc_transaction(unit, buf, 12, buf, 12, in avc_audio_set_selector()
31 BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | in avc_audio_set_selector()
32 BIT(6) | BIT(7) | BIT(8)); in avc_audio_set_selector()
36 err = -EIO; in avc_audio_set_selector()
38 err = -ENOSYS; in avc_audio_set_selector()
[all …]
/kernel/linux/linux-4.19/sound/firewire/bebob/
Dbebob_command.c2 * bebob_command.c - driver for BeBoB based devices
4 * Copyright (c) 2013-2014 Takashi Sakamoto
17 buf = kzalloc(12, GFP_KERNEL); in avc_audio_set_selector()
19 return -ENOMEM; in avc_audio_set_selector()
31 err = fcp_avc_transaction(unit, buf, 12, buf, 12, in avc_audio_set_selector()
32 BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | in avc_audio_set_selector()
33 BIT(6) | BIT(7) | BIT(8)); in avc_audio_set_selector()
37 err = -EIO; in avc_audio_set_selector()
39 err = -ENOSYS; in avc_audio_set_selector()
41 err = -EINVAL; in avc_audio_set_selector()
[all …]
/kernel/linux/linux-4.19/drivers/net/ethernet/mscc/
Docelot_dev.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
13 #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7)
14 #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6)
15 #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5)
16 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4)
17 #define DEV_CLOCK_CFG_PORT_RST BIT(3)
18 #define DEV_CLOCK_CFG_PHY_RST BIT(2)
24 #define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4)
25 #define DEV_PORT_MISC_FWD_PAUSE_ENA BIT(3)
26 #define DEV_PORT_MISC_FWD_CTRL_ENA BIT(2)
[all …]
Docelot_dev_gmii.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
13 #define DEV_GMII_PORT_MODE_CLOCK_CFG_MAC_TX_RST BIT(5)
14 #define DEV_GMII_PORT_MODE_CLOCK_CFG_MAC_RX_RST BIT(4)
15 #define DEV_GMII_PORT_MODE_CLOCK_CFG_PORT_RST BIT(3)
16 #define DEV_GMII_PORT_MODE_CLOCK_CFG_PHY_RST BIT(2)
22 #define DEV_GMII_PORT_MODE_PORT_MISC_MPLS_RX_ENA BIT(5)
23 #define DEV_GMII_PORT_MODE_PORT_MISC_FWD_ERROR_ENA BIT(4)
24 #define DEV_GMII_PORT_MODE_PORT_MISC_FWD_PAUSE_ENA BIT(3)
25 #define DEV_GMII_PORT_MODE_PORT_MISC_FWD_CTRL_ENA BIT(2)
26 #define DEV_GMII_PORT_MODE_PORT_MISC_GMII_LOOP_ENA BIT(1)
[all …]
Docelot_hsio.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
11 #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
12 #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
13 #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
14 #define HSIO_PLL5G_CFG0_DIV4 BIT(28)
15 #define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
25 #define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
26 #define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14)
27 #define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13)
28 #define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12)
[all …]
Docelot_ana.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
11 #define ANA_ANAGEFIL_B_DOM_EN BIT(22)
12 #define ANA_ANAGEFIL_B_DOM_VAL BIT(21)
13 #define ANA_ANAGEFIL_AGE_LOCKED BIT(20)
14 #define ANA_ANAGEFIL_PID_EN BIT(19)
18 #define ANA_ANAGEFIL_VID_EN BIT(13)
19 #define ANA_ANAGEFIL_VID_VAL(x) ((x) & GENMASK(12, 0))
20 #define ANA_ANAGEFIL_VID_VAL_M GENMASK(12, 0)
27 #define ANA_STORMLIMIT_CFG_STORM_UNIT BIT(2)
31 #define ANA_AUTOAGE_AGE_FAST BIT(21)
[all …]
/kernel/linux/linux-4.19/drivers/staging/sm750fb/
Dddk750_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 #define DE_STATE1_DE_ABORT BIT(0)
10 #define DE_STATE2_DE_FIFO_EMPTY BIT(3)
11 #define DE_STATE2_DE_STATUS_BUSY BIT(2)
12 #define DE_STATE2_DE_MEM_FIFO_EMPTY BIT(1)
20 #define SYSTEM_CTRL_PCI_BURST BIT(29)
21 #define SYSTEM_CTRL_PCI_MASTER BIT(25)
22 #define SYSTEM_CTRL_LATENCY_TIMER_OFF BIT(24)
23 #define SYSTEM_CTRL_DE_FIFO_EMPTY BIT(23)
24 #define SYSTEM_CTRL_DE_STATUS_BUSY BIT(22)
[all …]
/kernel/linux/linux-5.10/drivers/staging/sm750fb/
Dddk750_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 #define DE_STATE1_DE_ABORT BIT(0)
10 #define DE_STATE2_DE_FIFO_EMPTY BIT(3)
11 #define DE_STATE2_DE_STATUS_BUSY BIT(2)
12 #define DE_STATE2_DE_MEM_FIFO_EMPTY BIT(1)
20 #define SYSTEM_CTRL_PCI_BURST BIT(29)
21 #define SYSTEM_CTRL_PCI_MASTER BIT(25)
22 #define SYSTEM_CTRL_LATENCY_TIMER_OFF BIT(24)
23 #define SYSTEM_CTRL_DE_FIFO_EMPTY BIT(23)
24 #define SYSTEM_CTRL_DE_STATUS_BUSY BIT(22)
[all …]
/kernel/liteos_m/targets/riscv_nuclei_gd32vf103_soc_gcc/SoC/gd32vf103/Common/Include/
Dgd32vf103_dac.h5 \version 2019-6-5, V1.0.0, firmware for GD32VF103
50 #define DAC0_R12DH REG32(DAC + 0x08U) /*!< DAC0 12-bit right-aligned data holding re…
51 #define DAC0_L12DH REG32(DAC + 0x0CU) /*!< DAC0 12-bit left-aligned data holding reg…
52 #define DAC0_R8DH REG32(DAC + 0x10U) /*!< DAC0 8-bit right-aligned data holding reg…
53 #define DAC1_R12DH REG32(DAC + 0x14U) /*!< DAC1 12-bit right-aligned data holding re…
54 #define DAC1_L12DH REG32(DAC + 0x18U) /*!< DAC1 12-bit left-aligned data holding reg…
55 #define DAC1_R8DH REG32(DAC + 0x1CU) /*!< DAC1 8-bit right-aligned data holding reg…
56 #define DACC_R12DH REG32(DAC + 0x20U) /*!< DAC concurrent mode 12-bit right-aligned …
57 #define DACC_L12DH REG32(DAC + 0x24U) /*!< DAC concurrent mode 12-bit left-aligned d…
58 #define DACC_R8DH REG32(DAC + 0x28U) /*!< DAC concurrent mode 8-bit right-aligned d…
[all …]
Dgd32vf103_gpio.h5 \version 2019-06-5, V1.0.0, firmware for GD32VF103
59 #define GPIO_BOP(gpiox) REG32((gpiox) + 0x10U) /*!< GPIO port bit operation register …
60 #define GPIO_BC(gpiox) REG32((gpiox) + 0x14U) /*!< GPIO bit clear register */
80 #define GPIO_CTL0_MD3 BITS(12, 13) /*!< port 3 mode bits */
98 #define GPIO_CTL1_MD11 BITS(12, 13) /*!< port 11 mode bits */
100 #define GPIO_CTL1_MD12 BITS(16, 17) /*!< port 12 mode bits */
101 #define GPIO_CTL1_CTL12 BITS(18, 19) /*!< pin 12 configuration bits */
110 #define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */
111 #define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */
112 #define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtw88/
Drtw8821c.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
21 ether_addr_copy(efuse->addr, map->e.mac_addr); in rtw8821ce_efuse_parsing()
26 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8821c_read_efuse()
32 efuse->rfe_option = map->rfe_option; in rtw8821c_read_efuse()
33 efuse->rf_board_option = map->rf_board_option; in rtw8821c_read_efuse()
34 efuse->crystal_cap = map->xtal_k; in rtw8821c_read_efuse()
35 efuse->pa_type_2g = map->pa_type; in rtw8821c_read_efuse()
36 efuse->pa_type_5g = map->pa_type; in rtw8821c_read_efuse()
37 efuse->lna_type_2g = map->lna_type_2g[0]; in rtw8821c_read_efuse()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/i2c/
Dtda1997x.txt1 Device-Tree bindings for the NXP TDA1997x HDMI receiver
6 - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4]
7 - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4]
8 - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4]
9 - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2]
10 - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]
11 - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
12 - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
13 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
16 - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0]
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/media/i2c/
Dtda1997x.txt1 Device-Tree bindings for the NXP TDA1997x HDMI receiver
6 - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4]
7 - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4]
8 - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4]
9 - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2]
10 - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]
11 - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
12 - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
13 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
16 - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0]
[all …]
/kernel/linux/linux-5.10/arch/arm64/include/asm/
Dsysreg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
19 * [20-19] : Op0
20 * [18-16] : Op1
21 * [15-12] : CRn
22 * [11-8] : CRm
23 * [7-5] : Op2
29 #define CRn_shift 12
80 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
232 #define SYS_PAR_EL1_F BIT(0)
246 #define SYS_PMSIDR_EL1_MAXSIZE_SHIFT 12
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/tve200/
Dtve200_drm.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * Copyright (C) 2006-2008 Intel Corporation
28 /* Bits 2-31 are valid physical base addresses */
36 #define TVE200_INT_BUS_ERR BIT(7)
37 #define TVE200_INT_V_STATUS BIT(6) /* vertical blank */
38 #define TVE200_INT_V_NEXT_FRAME BIT(5)
39 #define TVE200_INT_U_NEXT_FRAME BIT(4)
40 #define TVE200_INT_Y_NEXT_FRAME BIT(3)
41 #define TVE200_INT_V_FIFO_UNDERRUN BIT(2)
42 #define TVE200_INT_U_FIFO_UNDERRUN BIT(1)
[all …]
/kernel/linux/linux-5.10/drivers/staging/comedi/drivers/
Dni_stc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Register descriptions for NI DAQ-STC chip
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1998-9 David A. Schleef <ds@schleef.org>
11 * DAQ-STC Technical Reference Manual
21 * Registers in the National Instruments DAQ-STC chip
25 #define NISTC_INTA_ACK_G0_GATE BIT(15)
26 #define NISTC_INTA_ACK_G0_TC BIT(14)
27 #define NISTC_INTA_ACK_AI_ERR BIT(13)
28 #define NISTC_INTA_ACK_AI_STOP BIT(12)
[all …]
/kernel/linux/linux-5.10/include/linux/mfd/
Dwl1273-core.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * include/linux/mfd/wl1273-core.h
17 #define WL1273_FM_DRIVER_NAME "wl1273-fm"
28 #define WL1273_MOST_MODE_SET 12
125 #define WL1273_MODE_RX BIT(0)
126 #define WL1273_MODE_TX BIT(1)
127 #define WL1273_MODE_OFF BIT(2)
128 #define WL1273_MODE_SUSPENDED BIT(3)
130 #define WL1273_RADIO_CHILD BIT(0)
131 #define WL1273_CODEC_CHILD BIT(1)
[all …]
/kernel/linux/linux-4.19/drivers/soc/mediatek/
Dmtk-scpsys.c24 #include <dt-bindings/power/mt2701-power.h>
25 #include <dt-bindings/power/mt2712-power.h>
26 #include <dt-bindings/power/mt6797-power.h>
27 #include <dt-bindings/power/mt7622-power.h>
28 #include <dt-bindings/power/mt7623a-power.h>
29 #include <dt-bindings/power/mt8173-power.h>
34 #define MTK_SCPD_ACTIVE_WAKEUP BIT(0)
35 #define MTK_SCPD_FWAIT_SRAM BIT(1)
36 #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x))
62 #define PWR_RST_B_BIT BIT(0)
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/tve200/
Dtve200_drm.h5 * Copyright (C) 2006-2008 Intel Corporation
20 /* Bits 2-31 are valid physical base addresses */
28 #define TVE200_INT_BUS_ERR BIT(7)
29 #define TVE200_INT_V_STATUS BIT(6) /* vertical blank */
30 #define TVE200_INT_V_NEXT_FRAME BIT(5)
31 #define TVE200_INT_U_NEXT_FRAME BIT(4)
32 #define TVE200_INT_Y_NEXT_FRAME BIT(3)
33 #define TVE200_INT_V_FIFO_UNDERRUN BIT(2)
34 #define TVE200_INT_U_FIFO_UNDERRUN BIT(1)
35 #define TVE200_INT_Y_FIFO_UNDERRUN BIT(0)
[all …]
/kernel/linux/linux-4.19/drivers/staging/comedi/drivers/
Dni_stc.h1 // SPDX-License-Identifier: GPL-2.0+
3 * Register descriptions for NI DAQ-STC chip
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1998-9 David A. Schleef <ds@schleef.org>
11 * DAQ-STC Technical Reference Manual
20 * Registers in the National Instruments DAQ-STC chip
24 #define NISTC_INTA_ACK_G0_GATE BIT(15)
25 #define NISTC_INTA_ACK_G0_TC BIT(14)
26 #define NISTC_INTA_ACK_AI_ERR BIT(13)
27 #define NISTC_INTA_ACK_AI_STOP BIT(12)
[all …]

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