Searched +full:16 +full:- +full:bit (Results 1 – 25 of 1110) sorted by relevance
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| /kernel/linux/linux-5.10/drivers/mtd/nand/raw/ |
| D | nand_ids.c | 1 // SPDX-License-Identifier: GPL-2.0-only
29 {"TC58NVG0S3E 1G 3.3V 8-bit",
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
38 {"TC58NVG3S0F 8G 3.3V 8-bit",
41 {"TC58NVG5D2 32G 3.3V 8-bit",
44 {"TC58NVG6D2 64G 3.3V 8-bit",
47 {"SDTNRGAMA 64G 3.3V 8-bit",
50 {"H27UCG8T2ATR-BC 64G 3.3V 8-bit",
54 {"TH58NVG2S3HBAI4 4G 3.3V 8-bit",
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| /kernel/linux/linux-4.19/drivers/mtd/nand/raw/ |
| D | nand_ids.c | 31 {"TC58NVG0S3E 1G 3.3V 8-bit",
35 {"TC58NVG2S0F 4G 3.3V 8-bit",
38 {"TC58NVG2S0H 4G 3.3V 8-bit",
41 {"TC58NVG3S0F 8G 3.3V 8-bit",
44 {"TC58NVG5D2 32G 3.3V 8-bit",
47 {"TC58NVG6D2 64G 3.3V 8-bit",
50 {"SDTNRGAMA 64G 3.3V 8-bit",
53 {"H27UCG8T2ATR-BC 64G 3.3V 8-bit",
58 LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, SZ_8K, SP_OPTIONS),
59 LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),
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| /kernel/linux/linux-4.19/drivers/staging/sm750fb/ |
| D | ddk750_reg.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 #define DE_STATE1_DE_ABORT BIT(0)
10 #define DE_STATE2_DE_FIFO_EMPTY BIT(3)
11 #define DE_STATE2_DE_STATUS_BUSY BIT(2)
12 #define DE_STATE2_DE_MEM_FIFO_EMPTY BIT(1)
20 #define SYSTEM_CTRL_PCI_BURST BIT(29)
21 #define SYSTEM_CTRL_PCI_MASTER BIT(25)
22 #define SYSTEM_CTRL_LATENCY_TIMER_OFF BIT(24)
23 #define SYSTEM_CTRL_DE_FIFO_EMPTY BIT(23)
24 #define SYSTEM_CTRL_DE_STATUS_BUSY BIT(22)
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| D | sm750_accel.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
25 #define DE_SOURCE_WRAP BIT(31)
26 #define DE_SOURCE_X_K1_SHIFT 16
27 #define DE_SOURCE_X_K1_MASK (0x3fff << 16)
28 #define DE_SOURCE_X_K1_MONO_MASK (0x1f << 16)
32 #define DE_DESTINATION_WRAP BIT(31)
33 #define DE_DESTINATION_X_SHIFT 16
34 #define DE_DESTINATION_X_MASK (0x1fff << 16)
38 #define DE_DIMENSION_X_SHIFT 16
39 #define DE_DIMENSION_X_MASK (0x1fff << 16)
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| /kernel/linux/linux-5.10/drivers/staging/sm750fb/ |
| D | ddk750_reg.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
7 #define DE_STATE1_DE_ABORT BIT(0)
10 #define DE_STATE2_DE_FIFO_EMPTY BIT(3)
11 #define DE_STATE2_DE_STATUS_BUSY BIT(2)
12 #define DE_STATE2_DE_MEM_FIFO_EMPTY BIT(1)
20 #define SYSTEM_CTRL_PCI_BURST BIT(29)
21 #define SYSTEM_CTRL_PCI_MASTER BIT(25)
22 #define SYSTEM_CTRL_LATENCY_TIMER_OFF BIT(24)
23 #define SYSTEM_CTRL_DE_FIFO_EMPTY BIT(23)
24 #define SYSTEM_CTRL_DE_STATUS_BUSY BIT(22)
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| D | sm750_accel.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
25 #define DE_SOURCE_WRAP BIT(31)
26 #define DE_SOURCE_X_K1_SHIFT 16
27 #define DE_SOURCE_X_K1_MASK (0x3fff << 16)
28 #define DE_SOURCE_X_K1_MONO_MASK (0x1f << 16)
32 #define DE_DESTINATION_WRAP BIT(31)
33 #define DE_DESTINATION_X_SHIFT 16
34 #define DE_DESTINATION_X_MASK (0x1fff << 16)
38 #define DE_DIMENSION_X_SHIFT 16
39 #define DE_DIMENSION_X_MASK (0x1fff << 16)
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| /kernel/linux/linux-5.10/drivers/media/platform/omap3isp/ |
| D | ispreg.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * TI OMAP3 ISP - Registers definitions
48 #define ISPCCP2_SYSCONFIG_SOFT_RESET BIT(1)
58 #define ISPCCP2_SYSSTATUS_RESET_DONE BIT(0)
61 #define ISPCCP2_LC01_IRQSTATUS_LC0_FS_IRQ BIT(11)
62 #define ISPCCP2_LC01_IRQSTATUS_LC0_LE_IRQ BIT(10)
63 #define ISPCCP2_LC01_IRQSTATUS_LC0_LS_IRQ BIT(9)
64 #define ISPCCP2_LC01_IRQSTATUS_LC0_FE_IRQ BIT(8)
65 #define ISPCCP2_LC01_IRQSTATUS_LC0_COUNT_IRQ BIT(7)
66 #define ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ BIT(5)
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| /kernel/linux/linux-5.10/drivers/gpu/drm/mediatek/ |
| D | mtk_dpi_regs.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
10 #define EN BIT(0)
13 #define RST BIT(0)
16 #define INT_VSYNC_EN BIT(0)
17 #define INT_VDE_EN BIT(1)
18 #define INT_UNDERFLOW_EN BIT(2)
21 #define INT_VSYNC_STA BIT(0)
22 #define INT_VDE_STA BIT(1)
23 #define INT_UNDERFLOW_STA BIT(2)
26 #define BG_ENABLE BIT(0)
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| /kernel/linux/linux-5.10/include/soc/mscc/ |
| D | ocelot_dev.h | 1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
11 #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7)
12 #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6)
13 #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5)
14 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4)
15 #define DEV_CLOCK_CFG_PORT_RST BIT(3)
16 #define DEV_CLOCK_CFG_PHY_RST BIT(2)
20 #define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4)
21 #define DEV_PORT_MISC_FWD_PAUSE_ENA BIT(3)
22 #define DEV_PORT_MISC_FWD_CTRL_ENA BIT(2)
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| D | ocelot_hsio.h | 1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
85 #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
86 #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
87 #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
88 #define HSIO_PLL5G_CFG0_DIV4 BIT(28)
89 #define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
96 #define HSIO_PLL5G_CFG0_SELCPI(x) (((x) << 16) & GENMASK(17, 16))
97 #define HSIO_PLL5G_CFG0_SELCPI_M GENMASK(17, 16)
98 #define HSIO_PLL5G_CFG0_SELCPI_X(x) (((x) & GENMASK(17, 16)) >> 16)
99 #define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
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| /kernel/linux/linux-4.19/drivers/net/ethernet/mscc/ |
| D | ocelot_dev.h | 1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
13 #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7)
14 #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6)
15 #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5)
16 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4)
17 #define DEV_CLOCK_CFG_PORT_RST BIT(3)
18 #define DEV_CLOCK_CFG_PHY_RST BIT(2)
24 #define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4)
25 #define DEV_PORT_MISC_FWD_PAUSE_ENA BIT(3)
26 #define DEV_PORT_MISC_FWD_CTRL_ENA BIT(2)
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| D | ocelot_hsio.h | 1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
11 #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
12 #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
13 #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
14 #define HSIO_PLL5G_CFG0_DIV4 BIT(28)
15 #define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
22 #define HSIO_PLL5G_CFG0_SELCPI(x) (((x) << 16) & GENMASK(17, 16))
23 #define HSIO_PLL5G_CFG0_SELCPI_M GENMASK(17, 16)
24 #define HSIO_PLL5G_CFG0_SELCPI_X(x) (((x) & GENMASK(17, 16)) >> 16)
25 #define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
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| /kernel/linux/linux-4.19/drivers/net/ethernet/stmicro/stmmac/ |
| D | dwxgmac2.h | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
24 #define XGMAC_CONFIG_JD BIT(16)
25 #define XGMAC_CONFIG_TE BIT(0)
28 #define XGMAC_CONFIG_ARPEN BIT(31)
29 #define XGMAC_CONFIG_GPSL GENMASK(29, 16)
30 #define XGMAC_CONFIG_GPSL_SHIFT 16
31 #define XGMAC_CONFIG_S2KP BIT(11)
32 #define XGMAC_CONFIG_IPC BIT(9)
33 #define XGMAC_CONFIG_JE BIT(8)
34 #define XGMAC_CONFIG_WD BIT(7)
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| /kernel/linux/linux-5.10/drivers/net/ethernet/stmicro/stmmac/ |
| D | dwxgmac2.h | 1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
28 #define XGMAC_CONFIG_JD BIT(16)
29 #define XGMAC_CONFIG_TE BIT(0)
32 #define XGMAC_CONFIG_ARPEN BIT(31)
33 #define XGMAC_CONFIG_GPSL GENMASK(29, 16)
34 #define XGMAC_CONFIG_GPSL_SHIFT 16
38 #define XGMAC_CONFIG_S2KP BIT(11)
39 #define XGMAC_CONFIG_LM BIT(10)
40 #define XGMAC_CONFIG_IPC BIT(9)
41 #define XGMAC_CONFIG_JE BIT(8)
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| /kernel/linux/linux-5.10/drivers/media/platform/vsp1/ |
| D | vsp1_regs.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * vsp1_regs.h -- R-Car VSP1 Registers Definitions
13 /* -----------------------------------------------------------------------------
18 #define VI6_CMD_UPDHDR BIT(4)
19 #define VI6_CMD_STRCMD BIT(0)
28 #define VI6_SRESET_SRTS(n) BIT(n)
31 #define VI6_STATUS_FLD_STD(n) BIT((n) + 28)
32 #define VI6_STATUS_SYS_ACT(n) BIT((n) + 8)
35 #define VI6_WFP_IRQ_ENB_DFEE BIT(1)
36 #define VI6_WFP_IRQ_ENB_FREE BIT(0)
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| /kernel/linux/linux-4.19/drivers/net/ethernet/marvell/ |
| D | skge.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
137 /* B0_CTST 16 bit Control/Status register */
139 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
140 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
141 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
144 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
148 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
154 /* B0_LED 8 Bit LED register */
155 /* Bit 7.. 2: reserved */
159 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
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| /kernel/linux/linux-5.10/drivers/net/ethernet/marvell/ |
| D | skge.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
131 /* B0_CTST 16 bit Control/Status register */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
138 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
142 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
148 /* B0_LED 8 Bit LED register */
149 /* Bit 7.. 2: reserved */
153 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
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| /kernel/linux/linux-5.10/drivers/gpu/drm/vc4/ |
| D | vc4_regs.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2014-2015 Broadcom
27 ('D' << 16))
33 # define V3D_IDENT1_NSEM_MASK VC4_MASK(23, 16)
34 # define V3D_IDENT1_NSEM_SHIFT 16
47 # define V3D_L2CACTL_L2CCLR BIT(2)
48 # define V3D_L2CACTL_L2CDIS BIT(1)
49 # define V3D_L2CACTL_L2CENA BIT(0)
54 # define V3D_SLCACTL_T0CC_MASK VC4_MASK(19, 16)
55 # define V3D_SLCACTL_T0CC_SHIFT 16
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| /kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/mt7603/ |
| D | regs.h | 1 /* SPDX-License-Identifier: ISC */
28 #define MT_INT_RX_DONE(_n) BIT(_n)
31 #define MT_INT_TX_DONE(_n) BIT((_n) + 4)
33 #define MT_INT_RX_COHERENT BIT(20)
34 #define MT_INT_TX_COHERENT BIT(21)
35 #define MT_INT_MAC_IRQ3 BIT(27)
37 #define MT_INT_MCU_CMD BIT(30)
40 #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)
41 #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1)
42 #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2)
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| D | mac.h | 1 /* SPDX-License-Identifier: ISC */
9 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
10 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
13 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
14 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
15 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
30 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
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| /kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/mt7615/ |
| D | mac.h | 1 /* SPDX-License-Identifier: ISC */
11 #define MT_RXD0_PKT_FLAG GENMASK(19, 16)
14 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
15 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
17 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
18 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
19 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
20 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
36 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
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| /kernel/linux/linux-5.10/drivers/gpu/drm/v3d/ |
| D | v3d_regs.h | 1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2017-2018 Broadcom */
30 # define V3D_HUB_IDENT1_WITH_MSO BIT(19)
31 # define V3D_HUB_IDENT1_WITH_TSY BIT(18)
32 # define V3D_HUB_IDENT1_WITH_TFU BIT(17)
33 # define V3D_HUB_IDENT1_WITH_L3C BIT(16)
44 # define V3D_HUB_IDENT2_WITH_MMU BIT(8)
60 # define V3D_HUB_INT_MMU_WRV BIT(5)
61 # define V3D_HUB_INT_MMU_PTI BIT(4)
62 # define V3D_HUB_INT_MMU_CAP BIT(3)
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| /kernel/linux/linux-4.19/drivers/gpu/drm/vc4/ |
| D | vc4_regs.h | 2 * Copyright © 2014-2015 Broadcom
31 ('D' << 16))
37 # define V3D_IDENT1_NSEM_MASK VC4_MASK(23, 16)
38 # define V3D_IDENT1_NSEM_SHIFT 16
51 # define V3D_L2CACTL_L2CCLR BIT(2)
52 # define V3D_L2CACTL_L2CDIS BIT(1)
53 # define V3D_L2CACTL_L2CENA BIT(0)
58 # define V3D_SLCACTL_T0CC_MASK VC4_MASK(19, 16)
59 # define V3D_SLCACTL_T0CC_SHIFT 16
68 # define V3D_INT_SPILLUSE BIT(3)
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| /kernel/linux/linux-4.19/drivers/infiniband/hw/ocrdma/ |
| D | ocrdma_sli.h | 3 * Copyright (C) 2012-2015 Emulex. All rights reserved.
16 * - Redistributions of source code must retain the above copyright notice,
19 * - Redistributions in binary form must reproduce the above copyright
36 * linux-drivers@emulex.com
77 OCRDMA_CMD_QUERY_NSMR = 16,
122 #define OCRDMA_MAX_SGID 16
139 OCRDMA_DB_SQ_SHIFT = 16,
149 #define OCRDMA_DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
150 #define OCRDMA_DB_CQ_RING_ID_EXT_MASK 0x0C00 /* bits 10-11 of qid at 12-11 */
151 /* qid #2 msbits at 12-11 */
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| /kernel/linux/linux-5.10/drivers/infiniband/hw/ocrdma/ |
| D | ocrdma_sli.h | 3 * Copyright (C) 2012-2015 Emulex. All rights reserved.
16 * - Redistributions of source code must retain the above copyright notice,
19 * - Redistributions in binary form must reproduce the above copyright
36 * linux-drivers@emulex.com
77 OCRDMA_CMD_QUERY_NSMR = 16,
122 #define OCRDMA_MAX_SGID 16
139 OCRDMA_DB_SQ_SHIFT = 16,
149 #define OCRDMA_DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
150 #define OCRDMA_DB_CQ_RING_ID_EXT_MASK 0x0C00 /* bits 10-11 of qid at 12-11 */
151 /* qid #2 msbits at 12-11 */
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