Searched +full:29 +full:- +full:bit (Results 1 – 25 of 1035) sorted by relevance
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| /kernel/linux/linux-5.10/drivers/media/platform/exynos4-is/ |
| D | fimc-reg.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2010 - 2012 Samsung Electronics Co., Ltd.
13 #include "fimc-core.h"
17 #define FIMC_REG_CISRCFMT_ITU601_8BIT BIT(31)
18 #define FIMC_REG_CISRCFMT_ITU601_16BIT BIT(29)
26 #define FIMC_REG_CIWDOFST_OFF_EN BIT(31)
27 #define FIMC_REG_CIWDOFST_CLROVFIY BIT(30)
28 #define FIMC_REG_CIWDOFST_CLROVRLB BIT(29)
30 #define FIMC_REG_CIWDOFST_CLROVFICB BIT(15)
31 #define FIMC_REG_CIWDOFST_CLROVFICR BIT(14)
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| /kernel/linux/linux-5.10/drivers/staging/media/zoran/ |
| D | zr36057.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * zr36057.h - zr36057 register offsets
14 #define ZR36057_VFEHCR_HS_POL BIT(30)
20 #define ZR36057_VFEVCR_VS_POL BIT(30)
26 #define ZR36057_VFESPFR_EXT_FL BIT(26)
27 #define ZR36057_VFESPFR_TOP_FIELD BIT(25)
28 #define ZR36057_VFESPFR_VCLK_POL BIT(24)
47 #define ZR36057_VSSFGR_VID_OVF BIT(8)
48 #define ZR36057_VSSFGR_SNAP_SHOT BIT(1)
49 #define ZR36057_VSSFGR_FRAME_GRAB BIT(0)
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| /kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/mt7603/ |
| D | mac.h | 1 /* SPDX-License-Identifier: ISC */
7 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
10 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
13 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
14 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
15 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
30 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
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| /kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/mt7915/ |
| D | mac.h | 1 /* SPDX-License-Identifier: ISC */
14 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
15 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
30 #define MT_RXD1_NORMAL_GROUP_1 BIT(11)
31 #define MT_RXD1_NORMAL_GROUP_2 BIT(12)
32 #define MT_RXD1_NORMAL_GROUP_3 BIT(13)
33 #define MT_RXD1_NORMAL_GROUP_4 BIT(14)
34 #define MT_RXD1_NORMAL_GROUP_5 BIT(15)
37 #define MT_RXD1_NORMAL_CM BIT(23)
38 #define MT_RXD1_NORMAL_CLM BIT(24)
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| /kernel/linux/linux-5.10/drivers/media/platform/s3c-camif/ |
| D | camif-regs.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include "camif-core.h"
15 #include <media/drv-intf/s3c_camif.h>
19 * id = 0 - codec (FIMC C), 1 - preview (FIMC P).
24 #define CISRCFMT_ITU601_8BIT BIT(31)
35 #define CIWDOFST_WINOFSEN BIT(31)
36 #define CIWDOFST_CLROVCOFIY BIT(30)
37 #define CIWDOFST_CLROVRLB_PR BIT(28)
38 /* #define CIWDOFST_CLROVPRFIY BIT(27) */
39 #define CIWDOFST_CLROVCOFICB BIT(15)
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| /kernel/linux/linux-5.10/drivers/usb/dwc2/ |
| D | hw.h | 1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
3 * hw.h - DesignWare HS OTG Controller hardware definitions
5 * Copyright 2004-2013 Synopsys, Inc.
16 * 3. The names of the above-listed copyright holders may not be used
44 #define GOTGCTL_CHIRPEN BIT(27)
47 #define GOTGCTL_OTGVER BIT(20)
48 #define GOTGCTL_BSESVLD BIT(19)
49 #define GOTGCTL_ASESVLD BIT(18)
50 #define GOTGCTL_DBNC_SHORT BIT(17)
51 #define GOTGCTL_CONID_B BIT(16)
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| /kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/mt7615/ |
| D | mac.h | 1 /* SPDX-License-Identifier: ISC */
12 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
15 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
17 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
18 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
19 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
20 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
36 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
37 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
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| /kernel/linux/linux-4.19/drivers/usb/dwc2/ |
| D | hw.h | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * hw.h - DesignWare HS OTG Controller hardware definitions
5 * Copyright 2004-2013 Synopsys, Inc.
16 * 3. The names of the above-listed copyright holders may not be used
44 #define GOTGCTL_CHIRPEN BIT(27)
47 #define GOTGCTL_OTGVER BIT(20)
48 #define GOTGCTL_BSESVLD BIT(19)
49 #define GOTGCTL_ASESVLD BIT(18)
50 #define GOTGCTL_DBNC_SHORT BIT(17)
51 #define GOTGCTL_CONID_B BIT(16)
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| /kernel/linux/linux-5.10/Documentation/core-api/ |
| D | packing.rst | 6 -----------------
10 One can memory-map a pointer to a carefully crafted struct over the hardware
15 definitions from the hardware documentation into bit field indices for the
18 (sometimes even 64 bit ones). This creates the inconvenience of having to
23 were performed byte-by-byte. Also the code can easily get cluttered, and the
24 high-level idea might get lost among the many bit shifts required.
25 Many drivers take the bit-shifting approach and then attempt to reduce the
30 ------------
34 - Packing a CPU-usable number into a memory buffer (with hardware
36 - Unpacking a memory buffer (which has hardware constraints/quirks)
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| /kernel/linux/linux-4.19/drivers/net/ethernet/stmicro/stmmac/ |
| D | dwxgmac2.h | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
17 #define XGMAC_CONFIG_SS_OFF 29
18 #define XGMAC_CONFIG_SS_MASK GENMASK(30, 29)
24 #define XGMAC_CONFIG_JD BIT(16)
25 #define XGMAC_CONFIG_TE BIT(0)
28 #define XGMAC_CONFIG_ARPEN BIT(31)
29 #define XGMAC_CONFIG_GPSL GENMASK(29, 16)
31 #define XGMAC_CONFIG_S2KP BIT(11)
32 #define XGMAC_CONFIG_IPC BIT(9)
33 #define XGMAC_CONFIG_JE BIT(8)
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| /kernel/linux/linux-4.19/drivers/usb/chipidea/ |
| D | bits.h | 1 // SPDX-License-Identifier: GPL-2.0
3 * bits.h - register bits of the ChipIdea USB IP core
5 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
17 * For 1.x revision, bit24 - bit31 are reserved
18 * For 2.x revision, bit25 - bit28 are 0x2
23 #define CIVERSION (0x7 << 29)
29 #define HCCPARAMS_LEN BIT(17)
33 #define DCCPARAMS_DC BIT(7)
34 #define DCCPARAMS_HC BIT(8)
37 #define TESTMODE_FORCE BIT(0)
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| /kernel/linux/linux-5.10/drivers/usb/chipidea/ |
| D | bits.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * bits.h - register bits of the ChipIdea USB IP core
5 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
17 * For 1.x revision, bit24 - bit31 are reserved
18 * For 2.x revision, bit25 - bit28 are 0x2
23 #define CIVERSION (0x7 << 29)
29 #define HCCPARAMS_LEN BIT(17)
33 #define DCCPARAMS_DC BIT(7)
34 #define DCCPARAMS_HC BIT(8)
37 #define TESTMODE_FORCE BIT(0)
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| /kernel/linux/linux-5.10/drivers/media/platform/ti-vpe/ |
| D | cal_regs.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
20 * LDOs on the device are disabled if CSI-2 module is powered on
25 * Errata does not apply when CSI-2 module is powered off
30 * which is essentially CSI2 REG10 bit 6:
35 #define DRA72_CAL_PRE_ES2_LDO_DISABLE BIT(0)
120 #define CAL_HL_HWINFO_NPPI_CTXS0_MASK GENMASK(29, 28)
127 #define CAL_HL_SYSCONFIG_SOFTRESET_MASK BIT(0)
138 #define CAL_HL_IRQ_EOI_LINE_NUMBER_MASK BIT(0)
142 #define CAL_HL_IRQ_MASK(m) BIT(m)
144 #define CAL_HL_IRQ_OCPO_ERR_MASK BIT(6)
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| /kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/ |
| D | mt76x02_dma.h | 1 /* SPDX-License-Identifier: ISC */
13 #define MT_TXD_INFO_NEXT_VLD BIT(16)
14 #define MT_TXD_INFO_TX_BURST BIT(17)
15 #define MT_TXD_INFO_80211 BIT(19)
16 #define MT_TXD_INFO_TSO BIT(20)
17 #define MT_TXD_INFO_CSO BIT(21)
18 #define MT_TXD_INFO_WIV BIT(24)
20 #define MT_TXD_INFO_DPORT GENMASK(29, 27)
24 #define MT_RX_FCE_INFO_SELF_GEN BIT(15)
27 #define MT_RX_FCE_INFO_PCIE_INTR BIT(24)
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| /kernel/linux/linux-4.19/drivers/gpu/drm/vc4/ |
| D | vc4_regs.h | 2 * Copyright © 2014-2015 Broadcom
51 # define V3D_L2CACTL_L2CCLR BIT(2)
52 # define V3D_L2CACTL_L2CDIS BIT(1)
53 # define V3D_L2CACTL_L2CENA BIT(0)
68 # define V3D_INT_SPILLUSE BIT(3)
69 # define V3D_INT_OUTOMEM BIT(2)
70 # define V3D_INT_FLDONE BIT(1)
71 # define V3D_INT_FRDONE BIT(0)
76 # define V3D_CTRSTA BIT(15)
77 # define V3D_CTSEMA BIT(12)
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| /kernel/linux/linux-5.10/drivers/gpu/drm/vc4/ |
| D | vc4_regs.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2014-2015 Broadcom
47 # define V3D_L2CACTL_L2CCLR BIT(2)
48 # define V3D_L2CACTL_L2CDIS BIT(1)
49 # define V3D_L2CACTL_L2CENA BIT(0)
64 # define V3D_INT_SPILLUSE BIT(3)
65 # define V3D_INT_OUTOMEM BIT(2)
66 # define V3D_INT_FLDONE BIT(1)
67 # define V3D_INT_FRDONE BIT(0)
72 # define V3D_CTRSTA BIT(15)
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| /kernel/linux/linux-5.10/Documentation/ABI/testing/ |
| D | sysfs-class-mtd | 3 KernelVersion: 2.6.29
4 Contact: linux-mtd@lists.infradead.org
11 KernelVersion: 2.6.29
12 Contact: linux-mtd@lists.infradead.org
21 KernelVersion: 2.6.29
22 Contact: linux-mtd@lists.infradead.org
24 These directories provide the corresponding read-only device
29 KernelVersion: 2.6.29
30 Contact: linux-mtd@lists.infradead.org
34 read-write device so <minor> will be even.
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| /kernel/linux/linux-4.19/Documentation/ABI/testing/ |
| D | sysfs-class-mtd | 3 KernelVersion: 2.6.29
4 Contact: linux-mtd@lists.infradead.org
11 KernelVersion: 2.6.29
12 Contact: linux-mtd@lists.infradead.org
21 KernelVersion: 2.6.29
22 Contact: linux-mtd@lists.infradead.org
24 These directories provide the corresponding read-only device
29 KernelVersion: 2.6.29
30 Contact: linux-mtd@lists.infradead.org
34 read-write device so <minor> will be even.
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| /kernel/linux/linux-5.10/drivers/net/ethernet/stmicro/stmmac/ |
| D | dwxgmac2.h | 1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
17 #define XGMAC_CONFIG_SS_OFF 29
18 #define XGMAC_CONFIG_SS_MASK GENMASK(31, 29)
28 #define XGMAC_CONFIG_JD BIT(16)
29 #define XGMAC_CONFIG_TE BIT(0)
32 #define XGMAC_CONFIG_ARPEN BIT(31)
33 #define XGMAC_CONFIG_GPSL GENMASK(29, 16)
38 #define XGMAC_CONFIG_S2KP BIT(11)
39 #define XGMAC_CONFIG_LM BIT(10)
40 #define XGMAC_CONFIG_IPC BIT(9)
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| /kernel/linux/linux-5.10/drivers/net/ethernet/emulex/benet/ |
| D | be_hw.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2005-2016 Broadcom.
7 * linux-drivers@emulex.com
18 * for the MAILBOX structure. Software must poll the ready bit until this
20 * bits in the address. It must poll the ready bit until the command is
25 #define MPU_MAILBOX_DB_RDY_MASK 0x1 /* bit 0 */
26 #define MPU_MAILBOX_DB_HI_MASK 0x2 /* bit 1 */
33 #define SLIPORT_SEMAPHORE_OFFSET_SH 0x94 /* PCI-CFG offset */
40 #define SLIPORT_SOFTRESET_SR_MASK 0x00000080 /* SR bit */
44 #define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */
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| /kernel/linux/linux-4.19/drivers/net/ethernet/emulex/benet/ |
| D | be_hw.h | 2 * Copyright (C) 2005-2016 Broadcom.
11 * linux-drivers@emulex.com
22 * for the MAILBOX structure. Software must poll the ready bit until this
24 * bits in the address. It must poll the ready bit until the command is
29 #define MPU_MAILBOX_DB_RDY_MASK 0x1 /* bit 0 */
30 #define MPU_MAILBOX_DB_HI_MASK 0x2 /* bit 1 */
37 #define SLIPORT_SEMAPHORE_OFFSET_SH 0x94 /* PCI-CFG offset */
44 #define SLIPORT_SOFTRESET_SR_MASK 0x00000080 /* SR bit */
48 #define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */
83 * atomically without having to arbitrate for the PCI Interrupt Disable bit
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| /kernel/linux/linux-4.19/Documentation/ |
| D | robust-futex-ABI.txt | 43 consisting of three words. Each word is 32 bits on 32 bit arch's, or 64
44 bits on 64 bit arch's, and local byte order. Each thread should have
47 If a thread is running in 32 bit compatibility mode on a 64 native arch
48 kernel, then it can actually have two such structures - one using 32 bit
49 words for 32 bit compatibility mode, and one using 64 bit words for 64
50 bit native mode. The kernel, if it is a 64 bit kernel supporting 32 bit
63 is always a 32 bit word, unlike the other words above. The 'lock
65 of the thread holding the lock in the bottom 29 bits. See further
79 The 'lock word' is always 32 bits, and is intended to be the same 32 bit
89 the kernel will walk this list, mark any such locks with a bit
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| /kernel/linux/linux-5.10/drivers/net/ethernet/cortina/ |
| D | gemini.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
6 * Copyright (C) 2010 Michał Mirosław <mirq-linux@rere.qmqm.pl>
49 * GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
58 #define __RWPTR_PREV(x, mask) (((unsigned int)(x) - 1) & (mask))
59 #define __RWPTR_DISTANCE(r, w, mask) (((unsigned int)(w) - (r)) & (mask))
60 #define __RWPTR_MASK(order) ((1 << (order)) - 1)
200 #define GMAC1_TXDERR_INT_BIT BIT(31)
201 #define GMAC1_TXPERR_INT_BIT BIT(30)
202 #define GMAC0_TXDERR_INT_BIT BIT(29)
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| /kernel/linux/linux-4.19/drivers/net/ethernet/cortina/ |
| D | gemini.h | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
6 * Copyright (C) 2010 Michał Mirosław <mirq-linux@rere.qmqm.pl>
49 * GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
58 #define __RWPTR_PREV(x, mask) (((unsigned int)(x) - 1) & (mask))
59 #define __RWPTR_DISTANCE(r, w, mask) (((unsigned int)(w) - (r)) & (mask))
60 #define __RWPTR_MASK(order) ((1 << (order)) - 1)
200 #define GMAC1_TXDERR_INT_BIT BIT(31)
201 #define GMAC1_TXPERR_INT_BIT BIT(30)
202 #define GMAC0_TXDERR_INT_BIT BIT(29)
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| /kernel/linux/linux-4.19/drivers/gpu/drm/sun4i/ |
| D | sun8i_dw_hdmi.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
16 #define SUN8I_HDMI_PHY_DBG_CTRL_PX_LOCK BIT(0)
18 #define SUN8I_HDMI_PHY_DBG_CTRL_POL_NHSYNC BIT(8)
19 #define SUN8I_HDMI_PHY_DBG_CTRL_POL_NVSYNC BIT(9)
24 #define SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN BIT(31)
33 #define SUN8I_HDMI_PHY_ANA_CFG1_REG_SWI BIT(31)
34 #define SUN8I_HDMI_PHY_ANA_CFG1_REG_PWEND BIT(30)
35 #define SUN8I_HDMI_PHY_ANA_CFG1_REG_PWENC BIT(29)
36 #define SUN8I_HDMI_PHY_ANA_CFG1_REG_CALSW BIT(28)
39 #define SUN8I_HDMI_PHY_ANA_CFG1_AMP_OPT BIT(23)
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