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/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dorion5x-netgear-wnr854t.dts9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include "orion5x-mv88f5181.dtsi"
16 model = "Netgear WNR854-t";
17 compatible = "netgear,wnr854t", "marvell,orion5x-88f5181",
28 stdout-path = "serial0:115200n8";
37 gpio-keys {
38 compatible = "gpio-keys";
39 pinctrl-0 = <&pmx_reset_button>;
[all …]
Dmoxart-uc7112lx.dts1 /* moxart-uc7112lx.dts - Device Tree file for MOXA UC-7112-LX
8 /dts-v1/;
12 model = "MOXA UC-7112-LX";
13 compatible = "moxa,moxart-uc-7112-lx", "moxa,moxart";
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <12000000>;
29 compatible = "numonyx,js28f128", "cfi-flash";
31 bank-width = <2>;
32 #address-cells = <1>;
[all …]
Dkirkwood-guruplug-server-plus.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include "kirkwood-6281.dtsi"
9 …compatible = "globalscale,guruplug-server-plus", "globalscale,guruplug", "marvell,kirkwood-88f6281…
18 stdout-path = &uart0;
22 pinctrl: pin-controller@10000 {
23 pmx_led_health_r: pmx-led-health-r {
27 pmx_led_health_g: pmx-led-health-g {
31 pmx_led_wmode_r: pmx-led-wmode-r {
35 pmx_led_wmode_g: pmx-led-wmode-g {
[all …]
Dkeystone-k2e-evm.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
7 /dts-v1/;
10 #include "keystone-k2e.dtsi"
13 compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone";
16 reserved-memory {
17 #address-cells = <2>;
18 #size-cells = <2>;
21 dsp_common_memory: dsp-common-memory@81f800000 {
22 compatible = "shared-dma-pool";
[all …]
Dkeystone-k2l-evm.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
7 /dts-v1/;
10 #include "keystone-k2l.dtsi"
13 compatible = "ti,k2l-evm", "ti,k2l", "ti,keystone";
16 reserved-memory {
17 #address-cells = <2>;
18 #size-cells = <2>;
21 dsp_common_memory: dsp-common-memory@81f800000 {
22 compatible = "shared-dma-pool";
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dorion5x-netgear-wnr854t.dts9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include "orion5x-mv88f5181.dtsi"
16 model = "Netgear WNR854-t";
17 compatible = "netgear,wnr854t", "marvell,orion5x-88f5181",
29 stdout-path = "serial0:115200n8";
38 gpio-keys {
39 compatible = "gpio-keys";
40 pinctrl-0 = <&pmx_reset_button>;
[all …]
Daspeed-ast2600-evb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
4 /dts-v1/;
6 #include "aspeed-g6.dtsi"
29 ethphy1: ethernet-phy@0 {
30 compatible = "ethernet-phy-ieee802.3-c22";
38 ethphy2: ethernet-phy@0 {
39 compatible = "ethernet-phy-ieee802.3-c22";
47 ethphy3: ethernet-phy@0 {
48 compatible = "ethernet-phy-ieee802.3-c22";
56 phy-mode = "rgmii";
[all …]
Dmoxart-uc7112lx.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* moxart-uc7112lx.dts - Device Tree file for MOXA UC-7112-LX
7 /dts-v1/;
11 model = "MOXA UC-7112-LX";
12 compatible = "moxa,moxart-uc-7112-lx", "moxa,moxart";
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <12000000>;
28 compatible = "numonyx,js28f128", "cfi-flash";
30 bank-width = <2>;
[all …]
Dkirkwood-guruplug-server-plus.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include "kirkwood-6281.dtsi"
9 …compatible = "globalscale,guruplug-server-plus", "globalscale,guruplug", "marvell,kirkwood-88f6281…
18 stdout-path = &uart0;
22 pinctrl: pin-controller@10000 {
23 pmx_led_health_r: pmx-led-health-r {
27 pmx_led_health_g: pmx-led-health-g {
31 pmx_led_wmode_r: pmx-led-wmode-r {
35 pmx_led_wmode_g: pmx-led-wmode-g {
[all …]
Dkeystone-k2e-evm.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
7 /dts-v1/;
10 #include "keystone-k2e.dtsi"
13 compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone";
16 reserved-memory {
17 #address-cells = <2>;
18 #size-cells = <2>;
21 dsp_common_memory: dsp-common-memory@81f800000 {
22 compatible = "shared-dma-pool";
[all …]
Dkeystone-k2l-evm.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
7 /dts-v1/;
10 #include "keystone-k2l.dtsi"
13 compatible = "ti,k2l-evm", "ti,k2l", "ti,keystone";
16 reserved-memory {
17 #address-cells = <2>;
18 #size-cells = <2>;
21 dsp_common_memory: dsp-common-memory@81f800000 {
22 compatible = "shared-dma-pool";
[all …]
Dimx6sx-udoo-neo-basic.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "imx6sx-udoo-neo.dtsi"
21 phy-handle = <&ethphy1>;
25 #address-cells = <1>;
26 #size-cells = <0>;
28 ethphy1: ethernet-phy@0 {
29 compatible = "ethernet-phy-ieee802.3-c22";
/kernel/linux/linux-4.19/arch/mips/boot/dts/cavium-octeon/
Dubnt_e100.dts18 phy5: ethernet-phy@5 {
20 compatible = "ethernet-phy-ieee802.3-c22";
22 phy6: ethernet-phy@6 {
24 compatible = "ethernet-phy-ieee802.3-c22";
26 phy7: ethernet-phy@7 {
28 compatible = "ethernet-phy-ieee802.3-c22";
35 phy-handle = <&phy7>;
38 phy-handle = <&phy6>;
41 phy-handle = <&phy5>;
47 clock-frequency = <500000000>;
[all …]
/kernel/linux/linux-5.10/arch/mips/boot/dts/cavium-octeon/
Dubnt_e100.dts1 // SPDX-License-Identifier: GPL-2.0-only
15 phy5: ethernet-phy@5 {
17 compatible = "ethernet-phy-ieee802.3-c22";
19 phy6: ethernet-phy@6 {
21 compatible = "ethernet-phy-ieee802.3-c22";
23 phy7: ethernet-phy@7 {
25 compatible = "ethernet-phy-ieee802.3-c22";
32 phy-handle = <&phy7>;
33 rx-delay = <0>;
34 tx-delay = <0x10>;
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/net/
Dphy.txt5 - interrupts : interrupt specifier for the sole interrupt.
6 - reg : The ID number for the phy, usually a small integer
10 - compatible: Compatible list, may contain
11 "ethernet-phy-ieee802.3-c22" or "ethernet-phy-ieee802.3-c45" for
12 PHYs that implement IEEE802.3 clause 22 or IEEE802.3 clause 45
18 form: "ethernet-phy-idAAAA.BBBB" where
19 AAAA - The value of the 16 bit Phy Identifier 1 register as
20 4 hex digits. This is the chip vendor OUI bits 3:18
21 BBBB - The value of the 16 bit Phy Identifier 2 register as
28 - max-speed: Maximum PHY supported speed (10, 100, 1000...)
[all …]
Dhisilicon-hip04-net.txt6 - compatible: should be "hisilicon,hip04-mac".
7 - reg: address and length of the register set for the device.
8 - interrupts: interrupt for the device.
9 - port-handle: <phandle port channel>
13 - phy-mode: see ethernet.txt [1].
16 - phy-handle: see ethernet.txt [1].
27 - compatible: "hisilicon,hip04-ppe", "syscon".
28 - reg: address and length of the register set for the device.
35 - compatible: should be "hisilicon,mdio".
36 - Inherits from MDIO bus node binding [2]
[all …]
Dbrcm,bcmgenet.txt4 - compatible: should contain one of "brcm,genet-v1", "brcm,genet-v2",
5 "brcm,genet-v3", "brcm,genet-v4", "brcm,genet-v5".
6 - reg: address and length of the register set for the device
7 - interrupts and/or interrupts-extended: must be two cells, the first cell
10 optional third interrupt cell for Wake-on-LAN can be specified.
11 See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
13 - phy-mode: see ethernet.txt file in the same directory
14 - #address-cells: should be 1
15 - #size-cells: should be 1
18 - clocks: When provided, must be two phandles to the functional clocks nodes
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dhisilicon-hip04-net.txt6 - compatible: should be "hisilicon,hip04-mac".
7 - reg: address and length of the register set for the device.
8 - interrupts: interrupt for the device.
9 - port-handle: <phandle port channel>
14 - phy-mode: see ethernet.txt [1].
17 - phy-handle: see ethernet.txt [1].
28 - compatible: "hisilicon,hip04-ppe", "syscon".
29 - reg: address and length of the register set for the device.
36 - compatible: should be "hisilicon,mdio".
37 - Inherits from MDIO bus node binding [2]
[all …]
Dethernet-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
24 - $nodename
[all …]
Dbrcm,bcmgenet.txt4 - compatible: should contain one of "brcm,genet-v1", "brcm,genet-v2",
5 "brcm,genet-v3", "brcm,genet-v4", "brcm,genet-v5", "brcm,bcm2711-genet-v5".
6 - reg: address and length of the register set for the device
7 - interrupts and/or interrupts-extended: must be two cells, the first cell
10 optional third interrupt cell for Wake-on-LAN can be specified.
11 See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
13 - phy-mode: see ethernet.txt file in the same directory
14 - #address-cells: should be 1
15 - #size-cells: should be 1
18 - clocks: When provided, must be two phandles to the functional clocks nodes
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/samsung/sxgbe/
Dsxgbe_mdio.c1 // SPDX-License-Identifier: GPL-2.0-only
31 unsigned long fin_time = jiffies + 3 * HZ; /* 3 seconds */ in sxgbe_mdio_busy_wait()
39 return -EBUSY; in sxgbe_mdio_busy_wait()
48 ((sp->clk_csr & 0x7) << 19) | SXGBE_MII_BUSY; in sxgbe_mdio_ctrl_data()
49 writel(reg, sp->ioaddr + sp->hw->mii.data); in sxgbe_mdio_ctrl_data()
60 writel(reg, sp->ioaddr + sp->hw->mii.addr); in sxgbe_mdio_c45()
70 writel(1 << phyaddr, sp->ioaddr + SXGBE_MDIO_CLAUSE22_PORT_REG); in sxgbe_mdio_c22()
74 writel(reg, sp->ioaddr + sp->hw->mii.addr); in sxgbe_mdio_c22()
82 const struct mii_regs *mii = &sp->hw->mii; in sxgbe_mdio_access()
85 rc = sxgbe_mdio_busy_wait(sp->ioaddr, mii->data); in sxgbe_mdio_access()
[all …]
/kernel/linux/linux-4.19/drivers/net/ethernet/samsung/sxgbe/
Dsxgbe_mdio.c34 unsigned long fin_time = jiffies + 3 * HZ; /* 3 seconds */ in sxgbe_mdio_busy_wait()
42 return -EBUSY; in sxgbe_mdio_busy_wait()
51 ((sp->clk_csr & 0x7) << 19) | SXGBE_MII_BUSY; in sxgbe_mdio_ctrl_data()
52 writel(reg, sp->ioaddr + sp->hw->mii.data); in sxgbe_mdio_ctrl_data()
63 writel(reg, sp->ioaddr + sp->hw->mii.addr); in sxgbe_mdio_c45()
73 writel(1 << phyaddr, sp->ioaddr + SXGBE_MDIO_CLAUSE22_PORT_REG); in sxgbe_mdio_c22()
77 writel(reg, sp->ioaddr + sp->hw->mii.addr); in sxgbe_mdio_c22()
85 const struct mii_regs *mii = &sp->hw->mii; in sxgbe_mdio_access()
88 rc = sxgbe_mdio_busy_wait(sp->ioaddr, mii->data); in sxgbe_mdio_access()
95 /* Ports 0-3 only support C22. */ in sxgbe_mdio_access()
[all …]
/kernel/linux/linux-5.10/drivers/net/mdio/
Dmdio-cavium.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2009-2016 Cavium, Inc.
11 #include "mdio-cavium.h"
18 if (m == p->mode) in cavium_mdiobus_set_mode()
21 smi_clk.u64 = oct_mdio_readq(p->register_base + SMI_CLK); in cavium_mdiobus_set_mode()
24 oct_mdio_writeq(smi_clk.u64, p->register_base + SMI_CLK); in cavium_mdiobus_set_mode()
25 p->mode = m; in cavium_mdiobus_set_mode()
39 oct_mdio_writeq(smi_wr.u64, p->register_base + SMI_WR_DAT); in cavium_mdiobus_c45_addr()
47 oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD); in cavium_mdiobus_c45_addr()
54 smi_wr.u64 = oct_mdio_readq(p->register_base + SMI_WR_DAT); in cavium_mdiobus_c45_addr()
[all …]
/kernel/linux/linux-4.19/drivers/net/phy/
Dmdio-cavium.c6 * Copyright (C) 2009-2016 Cavium, Inc.
14 #include "mdio-cavium.h"
21 if (m == p->mode) in cavium_mdiobus_set_mode()
24 smi_clk.u64 = oct_mdio_readq(p->register_base + SMI_CLK); in cavium_mdiobus_set_mode()
27 oct_mdio_writeq(smi_clk.u64, p->register_base + SMI_CLK); in cavium_mdiobus_set_mode()
28 p->mode = m; in cavium_mdiobus_set_mode()
42 oct_mdio_writeq(smi_wr.u64, p->register_base + SMI_WR_DAT); in cavium_mdiobus_c45_addr()
50 oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD); in cavium_mdiobus_c45_addr()
57 smi_wr.u64 = oct_mdio_readq(p->register_base + SMI_WR_DAT); in cavium_mdiobus_c45_addr()
58 } while (smi_wr.s.pending && --timeout); in cavium_mdiobus_c45_addr()
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/allwinner/
Dsun50i-h6-orangepi-one-plus.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 #include "sun50i-h6-orangepi.dtsi"
9 compatible = "xunlong,orangepi-one-plus", "allwinner,sun50i-h6";
15 reg_gmac_3v3: gmac-3v3 {
16 compatible = "regulator-fixed";
17 regulator-name = "vcc-gmac-3v3";
18 regulator-min-microvolt = <3300000>;
19 regulator-max-microvolt = <3300000>;
20 startup-delay-us = <100000>;
21 enable-active-high;
[all …]

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