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/kernel/linux/linux-5.10/Documentation/admin-guide/media/
Dgspca-cardlist.rst1 .. SPDX-License-Identifier: GPL-2.0
8 - gspca_main: main driver
9 - gspca\_\ *driver*: subdriver module with *driver* as follows
19 spca501 040a:0002 Kodak DVC-325
24 spca500 041e:400a Creative PC-CAM 300
25 sunplus 041e:400b Creative PC-CAM 600
26 sunplus 041e:4012 PC-Cam350
41 sq930x 041e:4038 Creative Joy-IT
69 sn9c20x 0458:704c Genius i-Look 1321
70 sn9c20x 045e:00f4 LifeCam VX-6000 (SN9C20x + OV9650)
[all …]
/kernel/linux/linux-4.19/Documentation/media/v4l-drivers/
Dgspca-cardlist.rst6 - gspca_main: main driver
7 - gspca\_\ *driver*: subdriver module with *driver* as follows
17 spca501 040a:0002 Kodak DVC-325
22 spca500 041e:400a Creative PC-CAM 300
23 sunplus 041e:400b Creative PC-CAM 600
24 sunplus 041e:4012 PC-Cam350
39 sq930x 041e:4038 Creative Joy-IT
67 sn9c20x 0458:704c Genius i-Look 1321
68 sn9c20x 045e:00f4 LifeCam VX-6000 (SN9C20x + OV9650)
75 sunplus 0461:0821 Fujifilm MV-1
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/
Dbroadcom-bcm87xx.txt5 "ethernet-phy-ieee802.3-c45"
9 - broadcom,c45-reg-init : one of more sets of 4 cells. The first cell
18 ethernet-phy@5 {
20 compatible = "broadcom,bcm8706", "ethernet-phy-ieee802.3-c45";
21 interrupt-parent = <&gpio>;
28 broadcom,c45-reg-init = <1 0xc808 0xff8f 0x70>;
Dethernet-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
24 - $nodename
[all …]
Dmdio-mux-mmioreg.txt1 Properties for an MDIO bus multiplexer controlled by a memory-mapped device
3 This is a special case of a MDIO bus multiplexer. A memory-mapped device,
4 like an FPGA, is used to control which child bus is connected. The mdio-mux
5 node must be a child of the memory-mapped device. The driver currently only
6 supports devices with 8, 16 or 32-bit registers.
10 - compatible : string, must contain "mdio-mux-mmioreg"
12 - reg : integer, contains the offset of the register that controls the bus
16 - mux-mask : integer, contains an eight-bit mask that specifies which
18 'reg' property of each child mdio-mux node must be constrained by
23 The FPGA node defines a memory-mapped FPGA with a register space of 0x30 bytes.
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/net/
Dbroadcom-bcm87xx.txt5 "ethernet-phy-ieee802.3-c45"
9 - broadcom,c45-reg-init : one of more sets of 4 cells. The first cell
18 ethernet-phy@5 {
20 compatible = "broadcom,bcm8706", "ethernet-phy-ieee802.3-c45";
21 interrupt-parent = <&gpio>;
28 broadcom,c45-reg-init = <1 0xc808 0xff8f 0x70>;
Dmdio-mux-mmioreg.txt1 Properties for an MDIO bus multiplexer controlled by a memory-mapped device
3 This is a special case of a MDIO bus multiplexer. A memory-mapped device,
4 like an FPGA, is used to control which child bus is connected. The mdio-mux
5 node must be a child of the memory-mapped device. The driver currently only
6 supports devices with 8, 16 or 32-bit registers.
10 - compatible : string, must contain "mdio-mux-mmioreg"
12 - reg : integer, contains the offset of the register that controls the bus
16 - mux-mask : integer, contains an eight-bit mask that specifies which
18 'reg' property of each child mdio-mux node must be constrained by
23 The FPGA node defines a memory-mapped FPGA with a register space of 0x30 bytes.
[all …]
Dnixge.txt4 - compatible: Should be "ni,xge-enet-2.00"
5 - reg: Address and length of the register set for the device
6 - interrupts: Should contain tx and rx interrupt
7 - interrupt-names: Should be "rx" and "tx"
8 - phy-mode: See ethernet.txt file in the same directory.
9 - phy-handle: See ethernet.txt file in the same directory.
10 - nvmem-cells: Phandle of nvmem cell containing the MAC address
11 - nvmem-cell-names: Should be "address"
15 compatible = "ni,xge-enet-2.00";
18 nvmem-cells = <&eth1_addr>;
[all …]
/kernel/linux/linux-4.19/arch/powerpc/boot/dts/fsl/
Dt4240qds.dts4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "t4240si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
86 3 0 0xf 0xffdf0000 0x00008000>;
89 #address-cells = <1>;
90 #size-cells = <1>;
91 compatible = "cfi-flash";
94 bank-width = <2>;
[all …]
Db4860qds.dts4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "b4860si-pre.dtsi"
50 board-control@3,0 {
51 compatible = "fsl,b4860qds-fpga", "fsl,fpga-qixis";
58 phy-handle = <&phy_sgmii_1e>;
59 phy-connection-type = "sgmii";
63 phy-handle = <&phy_sgmii_1f>;
64 phy-connection-type = "sgmii";
68 phy-handle = <&phy_xaui_slot1>;
69 phy-connection-type = "xgmii";
[all …]
Dt2080rdb.dts2 * T2080PCIe-RDB Board Device Tree Source
4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
60 phy-handle = <&xg_aq1202_phy3>;
61 phy-connection-type = "xgmii";
65 phy-handle = <&xg_aq1202_phy4>;
66 phy-connection-type = "xgmii";
[all …]
Dt1024rdb.dts35 /include/ "t102xsi-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
48 reserved-memory {
49 #address-cells = <2>;
50 #size-cells = <2>;
53 bman_fbpr: bman-fbpr {
58 qman_fqd: qman-fqd {
63 qman_pfdr: qman-pfdr {
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/fsl/
Dt4240qds.dts4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "t4240si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
86 3 0 0xf 0xffdf0000 0x00008000>;
89 #address-cells = <1>;
90 #size-cells = <1>;
91 compatible = "cfi-flash";
94 bank-width = <2>;
[all …]
Db4860qds.dts4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "b4860si-pre.dtsi"
50 board-control@3,0 {
51 compatible = "fsl,b4860qds-fpga", "fsl,fpga-qixis";
58 phy-handle = <&phy_sgmii_1e>;
59 phy-connection-type = "sgmii";
63 phy-handle = <&phy_sgmii_1f>;
64 phy-connection-type = "sgmii";
68 phy-handle = <&phy_xaui_slot1>;
69 phy-connection-type = "xgmii";
[all …]
Dt2080rdb.dts2 * T2080PCIe-RDB Board Device Tree Source
4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
60 phy-handle = <&xg_aq1202_phy3>;
61 phy-connection-type = "xgmii";
65 phy-handle = <&xg_aq1202_phy4>;
66 phy-connection-type = "xgmii";
[all …]
Dt1024rdb.dts35 /include/ "t102xsi-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
48 reserved-memory {
49 #address-cells = <2>;
50 #size-cells = <2>;
53 bman_fbpr: bman-fbpr {
58 qman_fqd: qman-fqd {
63 qman_pfdr: qman-pfdr {
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/marvell/
Darmada-8040-mcbin.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-8040-mcbin.dtsi"
11 model = "Marvell 8040 MACCHIATOBin Double-shot";
12 compatible = "marvell,armada8040-mcbin-doubleshot",
13 "marvell,armada8040-mcbin", "marvell,armada8040",
14 "marvell,armada-ap806-quad", "marvell,armada-ap806";
20 phy0: ethernet-phy@0 {
21 compatible = "ethernet-phy-ieee802.3-c45";
26 phy8: ethernet-phy@8 {
27 compatible = "ethernet-phy-ieee802.3-c45";
[all …]
/kernel/linux/linux-5.10/drivers/net/phy/
Dbcm87xx.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2012 Cavium, Inc.
22 * broadcom,c45-reg-init property stored in the of_node for the phydev.
24 * broadcom,c45-reg-init = <devid reg mask value>,...;
28 * devid: which sub-device to use.
30 * mask: if non-zero, ANDed with existing register value.
40 if (!phydev->mdio.dev.of_node) in bcm87xx_of_reg_init()
43 paddr = of_get_property(phydev->mdio.dev.of_node, in bcm87xx_of_reg_init()
44 "broadcom,c45-reg-init", &len); in bcm87xx_of_reg_init()
52 while (paddr + 3 < paddr_end) { in bcm87xx_of_reg_init()
[all …]
/kernel/linux/linux-4.19/drivers/net/phy/
Dbcm87xx.c6 * Copyright (C) 2011 - 2012 Cavium, Inc.
25 * broadcom,c45-reg-init property stored in the of_node for the phydev.
27 * broadcom,c45-reg-init = <devid reg mask value>,...;
31 * devid: which sub-device to use.
33 * mask: if non-zero, ANDed with existing register value.
43 if (!phydev->mdio.dev.of_node) in bcm87xx_of_reg_init()
46 paddr = of_get_property(phydev->mdio.dev.of_node, in bcm87xx_of_reg_init()
47 "broadcom,c45-reg-init", &len); in bcm87xx_of_reg_init()
55 while (paddr + 3 < paddr_end) { in bcm87xx_of_reg_init()
89 phydev->supported = SUPPORTED_10000baseR_FEC; in bcm87xx_config_init()
[all …]
Dmdio-cavium.c6 * Copyright (C) 2009-2016 Cavium, Inc.
14 #include "mdio-cavium.h"
21 if (m == p->mode) in cavium_mdiobus_set_mode()
24 smi_clk.u64 = oct_mdio_readq(p->register_base + SMI_CLK); in cavium_mdiobus_set_mode()
25 smi_clk.s.mode = (m == C45) ? 1 : 0; in cavium_mdiobus_set_mode()
27 oct_mdio_writeq(smi_clk.u64, p->register_base + SMI_CLK); in cavium_mdiobus_set_mode()
28 p->mode = m; in cavium_mdiobus_set_mode()
38 cavium_mdiobus_set_mode(p, C45); in cavium_mdiobus_c45_addr()
42 oct_mdio_writeq(smi_wr.u64, p->register_base + SMI_WR_DAT); in cavium_mdiobus_c45_addr()
50 oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD); in cavium_mdiobus_c45_addr()
[all …]
/kernel/linux/linux-5.10/drivers/net/mdio/
Dmdio-cavium.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2009-2016 Cavium, Inc.
11 #include "mdio-cavium.h"
18 if (m == p->mode) in cavium_mdiobus_set_mode()
21 smi_clk.u64 = oct_mdio_readq(p->register_base + SMI_CLK); in cavium_mdiobus_set_mode()
22 smi_clk.s.mode = (m == C45) ? 1 : 0; in cavium_mdiobus_set_mode()
24 oct_mdio_writeq(smi_clk.u64, p->register_base + SMI_CLK); in cavium_mdiobus_set_mode()
25 p->mode = m; in cavium_mdiobus_set_mode()
35 cavium_mdiobus_set_mode(p, C45); in cavium_mdiobus_c45_addr()
39 oct_mdio_writeq(smi_wr.u64, p->register_base + SMI_WR_DAT); in cavium_mdiobus_c45_addr()
[all …]
Dmdio-cavium.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2009-2016 Cavium, Inc.
9 C45 enumerator
35 OCT_MDIO_BITFIELD_FIELD(u64 reserved_21_23:3,
52 OCT_MDIO_BITFIELD_FIELD(u64 reserved_13_15:3,
54 OCT_MDIO_BITFIELD_FIELD(u64 reserved_5_7:3,
111 #include <linux/io-64-nonatomic-lo-hi.h>
/kernel/linux/linux-5.10/drivers/net/ethernet/samsung/sxgbe/
Dsxgbe_mdio.c1 // SPDX-License-Identifier: GPL-2.0-only
31 unsigned long fin_time = jiffies + 3 * HZ; /* 3 seconds */ in sxgbe_mdio_busy_wait()
39 return -EBUSY; in sxgbe_mdio_busy_wait()
48 ((sp->clk_csr & 0x7) << 19) | SXGBE_MII_BUSY; in sxgbe_mdio_ctrl_data()
49 writel(reg, sp->ioaddr + sp->hw->mii.data); in sxgbe_mdio_ctrl_data()
60 writel(reg, sp->ioaddr + sp->hw->mii.addr); in sxgbe_mdio_c45()
70 writel(1 << phyaddr, sp->ioaddr + SXGBE_MDIO_CLAUSE22_PORT_REG); in sxgbe_mdio_c22()
74 writel(reg, sp->ioaddr + sp->hw->mii.addr); in sxgbe_mdio_c22()
82 const struct mii_regs *mii = &sp->hw->mii; in sxgbe_mdio_access()
85 rc = sxgbe_mdio_busy_wait(sp->ioaddr, mii->data); in sxgbe_mdio_access()
[all …]
/kernel/linux/linux-4.19/drivers/net/ethernet/samsung/sxgbe/
Dsxgbe_mdio.c34 unsigned long fin_time = jiffies + 3 * HZ; /* 3 seconds */ in sxgbe_mdio_busy_wait()
42 return -EBUSY; in sxgbe_mdio_busy_wait()
51 ((sp->clk_csr & 0x7) << 19) | SXGBE_MII_BUSY; in sxgbe_mdio_ctrl_data()
52 writel(reg, sp->ioaddr + sp->hw->mii.data); in sxgbe_mdio_ctrl_data()
63 writel(reg, sp->ioaddr + sp->hw->mii.addr); in sxgbe_mdio_c45()
73 writel(1 << phyaddr, sp->ioaddr + SXGBE_MDIO_CLAUSE22_PORT_REG); in sxgbe_mdio_c22()
77 writel(reg, sp->ioaddr + sp->hw->mii.addr); in sxgbe_mdio_c22()
85 const struct mii_regs *mii = &sp->hw->mii; in sxgbe_mdio_access()
88 rc = sxgbe_mdio_busy_wait(sp->ioaddr, mii->data); in sxgbe_mdio_access()
95 /* Ports 0-3 only support C22. */ in sxgbe_mdio_access()
[all …]
/kernel/linux/linux-4.19/drivers/of/
Dof_mdio.c31 * ethernet-phy-idAAAA.BBBB */
39 if (sscanf(cp, "ethernet-phy-id%4x.%4x", &upper, &lower) == 2) { in of_get_phy_id()
44 return -EINVAL; in of_get_phy_id()
56 "ethernet-phy-ieee802.3-c45"); in of_mdiobus_register_phy()
66 if (rc == -EPROBE_DEFER) { in of_mdiobus_register_phy()
71 phy->irq = rc; in of_mdiobus_register_phy()
72 mdio->irq[addr] = rc; in of_mdiobus_register_phy()
74 phy->irq = mdio->irq[addr]; in of_mdiobus_register_phy()
77 if (of_property_read_bool(child, "broken-turn-around")) in of_mdiobus_register_phy()
78 mdio->phy_ignore_ta_mask |= 1 << addr; in of_mdiobus_register_phy()
[all …]

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