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/kernel/linux/linux-5.10/arch/arm64/crypto/
Dchacha-neon-core.S4 * Copyright (C) 2016-2018 Linaro, Ltd. <ard.biesheuvel@linaro.org>
11 * ChaCha20 256-bit cipher algorithm, RFC7539, x64 SSSE3 functions
29 * chacha_permute - permute one block
31 * Permute one 64-byte block where the state matrix is stored in the four NEON
32 * registers v0-v3. It performs matrix operations on four words in parallel,
42 ld1 {v12.4s}, [x10]
45 // x0 += x1, x3 = rotl32(x3 ^ x0, 16)
46 add v0.4s, v0.4s, v1.4s
47 eor v3.16b, v3.16b, v0.16b
51 add v2.4s, v2.4s, v3.4s
[all …]
Dsm3-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * sm3-ce-core.S - SM3 secure hash using ARMv8.2 Crypto Extensions
11 .irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12
12 .set .Lv\b\().4s, \b
16 .inst 0xce60c000 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
20 .inst 0xce60c400 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
24 .inst 0xce400000 | .L\rd | (.L\rn << 5) | (.L\ra << 10) | (.L\rm << 16)
28 .inst 0xce408000 | .L\rd | (.L\rn << 5) | ((\imm2) << 12) | (.L\rm << 16)
32 .inst 0xce408400 | .L\rd | (.L\rn << 5) | ((\imm2) << 12) | (.L\rm << 16)
36 .inst 0xce408800 | .L\rd | (.L\rn << 5) | ((\imm2) << 12) | (.L\rm << 16)
[all …]
Dsha512-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha512-ce-core.S - core SHA-384/SHA-512 transform using v8 Crypto Extensions
15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19
21 .inst 0xce608000 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
25 .inst 0xce608400 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
33 .inst 0xce608800 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
37 * The SHA-512 round constants
40 .align 4
85 ld1 {v\rc1\().2d}, [x4], #16
88 ext v6.16b, v\i2\().16b, v\i3\().16b, #8
[all …]
Daes-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2013 - 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
9 .arch armv8-a+crypto
13 ld1 {v0.16b}, [x2]
14 ld1 {v1.4s}, [x0], #16
18 mov v3.16b, v1.16b
20 0: mov v2.16b, v1.16b
21 ld1 {v3.4s}, [x0], #16
22 1: aese v0.16b, v2.16b
23 aesmc v0.16b, v0.16b
[all …]
Dsha256-core.S_shipped1 // SPDX-License-Identifier: GPL-2.0
11 // Copyright 2014-2016 The OpenSSL Project Authors. All Rights Reserved.
30 // SHA256-hw SHA256(*) SHA512
31 // Apple A7 1.97 10.5 (+33%) 6.73 (-1%(**))
32 // Cortex-A53 2.38 15.5 (+115%) 10.0 (+150%(***))
33 // Cortex-A57 2.31 11.6 (+86%) 7.51 (+260%(***))
35 // X-Gene 20.0 (+100%) 12.8 (+300%(***))
40 // (**) The result is a trade-off: it's possible to improve it by
42 // on Cortex-A53 (or by 4 cycles per round).
43 // (***) Super-impressive coefficients over gcc-generated code are
[all …]
Dsha2-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * sha2-ce-core.S - core SHA-224/SHA-256 transform using v8 Crypto Extensions
12 .arch armv8-a+crypto
30 mov dg2v.16b, dg0v.16b
32 add t1.4s, v\s0\().4s, \rc\().4s
33 sha256h dg0q, dg1q, t0.4s
34 sha256h2 dg1q, dg2q, t0.4s
37 add t0.4s, v\s0\().4s, \rc\().4s
39 sha256h dg0q, dg1q, t1.4s
40 sha256h2 dg1q, dg2q, t1.4s
[all …]
Daes-ce-ccm-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * aesce-ccm-core.S - AES-CCM transform for ARMv8 with Crypto Extensions
5 * Copyright (C) 2013 - 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
12 .arch armv8-a+crypto
20 ld1 {v0.16b}, [x0] /* load mac */
22 sub w8, w8, #16
23 eor v1.16b, v1.16b, v1.16b
28 ext v1.16b, v1.16b, v1.16b, #1 /* rotate in the input bytes */
31 eor v0.16b, v0.16b, v1.16b
32 1: ld1 {v3.4s}, [x4] /* load first round key */
[all …]
/kernel/linux/linux-4.19/arch/arm64/crypto/
Dchacha20-neon-core.S2 * ChaCha20 256-bit cipher algorithm, RFC7539, arm64 NEON functions
11 * ChaCha20 256-bit cipher algorithm, RFC7539, x64 SSSE3 functions
40 ld1 {v0.4s-v3.4s}, [x0]
41 ld1 {v8.4s-v11.4s}, [x0]
42 ld1 {v12.4s}, [x3]
47 // x0 += x1, x3 = rotl32(x3 ^ x0, 16)
48 add v0.4s, v0.4s, v1.4s
49 eor v3.16b, v3.16b, v0.16b
53 add v2.4s, v2.4s, v3.4s
54 eor v4.16b, v1.16b, v2.16b
[all …]
Dsm3-ce-core.S2 * sm3-ce-core.S - SM3 secure hash using ARMv8.2 Crypto Extensions
14 .irp b, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12
15 .set .Lv\b\().4s, \b
19 .inst 0xce60c000 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
23 .inst 0xce60c400 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
27 .inst 0xce400000 | .L\rd | (.L\rn << 5) | (.L\ra << 10) | (.L\rm << 16)
31 .inst 0xce408000 | .L\rd | (.L\rn << 5) | ((\imm2) << 12) | (.L\rm << 16)
35 .inst 0xce408400 | .L\rd | (.L\rn << 5) | ((\imm2) << 12) | (.L\rm << 16)
39 .inst 0xce408800 | .L\rd | (.L\rn << 5) | ((\imm2) << 12) | (.L\rm << 16)
43 .inst 0xce408c00 | .L\rd | (.L\rn << 5) | ((\imm2) << 12) | (.L\rm << 16)
[all …]
Dsha512-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha512-ce-core.S - core SHA-384/SHA-512 transform using v8 Crypto Extensions
15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19
21 .inst 0xce608000 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
25 .inst 0xce608400 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
33 .inst 0xce608800 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
37 * The SHA-512 round constants
40 .align 4
85 ld1 {v\rc1\().2d}, [x4], #16
88 ext v6.16b, v\i2\().16b, v\i3\().16b, #8
[all …]
Dsha256-core.S_shipped1 // SPDX-License-Identifier: GPL-2.0
11 // Copyright 2014-2016 The OpenSSL Project Authors. All Rights Reserved.
30 // SHA256-hw SHA256(*) SHA512
31 // Apple A7 1.97 10.5 (+33%) 6.73 (-1%(**))
32 // Cortex-A53 2.38 15.5 (+115%) 10.0 (+150%(***))
33 // Cortex-A57 2.31 11.6 (+86%) 7.51 (+260%(***))
35 // X-Gene 20.0 (+100%) 12.8 (+300%(***))
40 // (**) The result is a trade-off: it's possible to improve it by
42 // on Cortex-A53 (or by 4 cycles per round).
43 // (***) Super-impressive coefficients over gcc-generated code are
[all …]
Dsha2-ce-core.S2 * sha2-ce-core.S - core SHA-224/SHA-256 transform using v8 Crypto Extensions
15 .arch armv8-a+crypto
33 mov dg2v.16b, dg0v.16b
35 add t1.4s, v\s0\().4s, \rc\().4s
36 sha256h dg0q, dg1q, t0.4s
37 sha256h2 dg1q, dg2q, t0.4s
40 add t0.4s, v\s0\().4s, \rc\().4s
42 sha256h dg0q, dg1q, t1.4s
43 sha256h2 dg1q, dg2q, t1.4s
48 sha256su0 v\s0\().4s, v\s1\().4s
[all …]
Daes-ce-core.S2 * Copyright (C) 2013 - 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
12 .arch armv8-a+crypto
16 ld1 {v0.16b}, [x2]
17 ld1 {v1.4s}, [x0], #16
21 mov v3.16b, v1.16b
23 0: mov v2.16b, v1.16b
24 ld1 {v3.4s}, [x0], #16
25 1: aese v0.16b, v2.16b
26 aesmc v0.16b, v0.16b
27 2: ld1 {v1.4s}, [x0], #16
[all …]
Daes-modes.S2 * linux/arch/arm64/crypto/aes-modes.S - chaining mode wrappers for AES
4 * Copyright (C) 2013 - 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
11 /* included by aes-ce.S and aes-neon.S */
14 .align 4
46 subs w23, w23, #4
48 ld1 {v0.16b-v3.16b}, [x20], #64 /* get 4 pt blocks */
50 st1 {v0.16b-v3.16b}, [x19], #64
54 adds w23, w23, #4
57 ld1 {v0.16b}, [x20], #16 /* get next pt block */
59 st1 {v0.16b}, [x19], #16
[all …]
Daes-ce-ccm-core.S2 * aesce-ccm-core.S - AES-CCM transform for ARMv8 with Crypto Extensions
4 * Copyright (C) 2013 - 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
15 .arch armv8-a+crypto
23 ld1 {v0.16b}, [x0] /* load mac */
25 sub w8, w8, #16
26 eor v1.16b, v1.16b, v1.16b
31 ext v1.16b, v1.16b, v1.16b, #1 /* rotate in the input bytes */
34 eor v0.16b, v0.16b, v1.16b
35 1: ld1 {v3.4s}, [x4] /* load first round key */
38 add x6, x4, #16
[all …]
/kernel/linux/linux-5.10/tools/testing/selftests/powerpc/lib/
Dreg.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
7 #include <ppc-asm.h>
11 /* Non volatile GPR - unsigned long buf[18] */
15 ld 16, 2*8(3)
17 ld 18, 4*8(3)
29 ld 30, 16*8(3)
37 std 16, 2*8(3)
39 std 18, 4*8(3)
51 std 30, 16*8(3)
56 /* Single Precision Float - float buf[32] */
[all …]
/kernel/linux/linux-4.19/tools/testing/selftests/powerpc/lib/
Dreg.S11 #include <ppc-asm.h>
15 /* Non volatile GPR - unsigned long buf[18] */
19 ld 16, 2*8(3)
21 ld 18, 4*8(3)
33 ld 30, 16*8(3)
41 std 16, 2*8(3)
43 std 18, 4*8(3)
55 std 30, 16*8(3)
60 /* Single Precision Float - float buf[32] */
62 lfs 0, 0*4(3)
[all …]
/kernel/linux/linux-5.10/arch/x86/crypto/
Dcast5-avx-x86_64-asm_64.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Cast5 Cipher 16-way parallel algorithm (AVX/x86_64)
6 * <Johannes.Goetzfried@informatik.stud.uni-erlangen.de>
14 .file "cast5-avx-x86_64-asm_64.S"
23 #define kr (16*4)
24 #define rr ((16*4)+16)
26 /* s-boxes */
33 16-way AVX cast5
88 shrq $16, src; \
89 movl s1(, RID1, 4), dst ## d; \
[all …]
/kernel/linux/linux-4.19/arch/x86/crypto/
Dcast5-avx-x86_64-asm_64.S2 * Cast5 Cipher 16-way parallel algorithm (AVX/x86_64)
5 * <Johannes.Goetzfried@informatik.stud.uni-erlangen.de>
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
29 .file "cast5-avx-x86_64-asm_64.S"
38 #define kr (16*4)
39 #define rr ((16*4)+16)
41 /* s-boxes */
48 16-way AVX cast5
103 shrq $16, src; \
104 movl s1(, RID1, 4), dst ## d; \
[all …]
Dmorus640-sse2-asm.S2 * SSE2 implementation of MORUS-640
4 * Copyright (c) 2017-2018 Ondrej Mosnacek <omosnacek@gmail.com>
5 * Copyright (C) 2017-2018 Red Hat, Inc. All rights reserved.
16 (i0 | (i1 << 2) | (i2 << 4) | (i3 << 6))
33 .align 16
41 .section .rodata.cst16.morus640_counter, "aM", @progbits, 16
42 .align 16
56 psrld $(32 - \b), \s0
64 * STATE[0-4] - input state
65 * MSG - message block
[all …]
/kernel/linux/linux-5.10/arch/csky/abiv1/
Dmemcpy.S1 /* SPDX-License-Identifier: GPL-2.0 */
2 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
25 cmplti r4, 4
36 cmplti r4, 16
42 ldw r5, (r3, 4)
46 stw r5, (r7, 4)
49 subi r4, 16
50 addi r3, 16
51 addi r7, 16
52 cmplti r4, 16
[all …]
/kernel/linux/linux-4.19/arch/alpha/lib/
Dev6-memset.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-memset.S
8 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
13 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
15 * E - either cluster
16 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
17 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
48 * undertake a major re-write to interleave the constant materialization
49 * with other parts of the fall-through code. This is important, even
55 bis $16,$16,$0 # E : return value
[all …]
/kernel/linux/linux-5.10/arch/alpha/lib/
Dev6-memset.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-memset.S
8 * 21264 version contributed by Rick Gorton <rick.gorton@alpha-processor.com>
13 * ftp.digital.com/pub/Digital/info/semiconductor/literature/dsc-library.html
15 * E - either cluster
16 * U - upper subcluster; U0 - subcluster U0; U1 - subcluster U1
17 * L - lower subcluster; L0 - subcluster L0; L1 - subcluster L1
48 * undertake a major re-write to interleave the constant materialization
49 * with other parts of the fall-through code. This is important, even
55 bis $16,$16,$0 # E : return value
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/vmwgfx/device_include/
Dsvga3d_surfacedefs.h1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
4 * Copyright 2008-2015 VMware, Inc., Palo Alto, CA., USA
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
29 * svga3d_surfacedefs.h --
49 * enum svga3d_block_desc - describes generic properties about formats.
74 SVGA3DBLOCKDESC_BUFFER = 1 << 4,
107 SVGA3DBLOCKDESC_SRGB = 1 << 16,
359 * struct svga3d_surface_desc - describes the actual pixel data.
388 {1, 1, 1}, 4, 4,
390 {{0}, {8}, {16}, {24}}},
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/vmwgfx/device_include/
Dsvga3d_surfacedefs.h1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
4 * Copyright 2008-2015 VMware, Inc., Palo Alto, CA., USA
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
29 * svga3d_surfacedefs.h --
49 * enum svga3d_block_desc - describes generic properties about formats.
74 SVGA3DBLOCKDESC_BUFFER = 1 << 4,
107 SVGA3DBLOCKDESC_SRGB = 1 << 16,
373 * struct svga3d_surface_desc - describes the actual pixel data.
402 {1, 1, 1}, 4, 4,
404 {{0}, {8}, {16}, {24}}},
[all …]

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