Searched +full:4 +full:c000000 (Results 1 – 25 of 84) sorted by relevance
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/ti/ |
| D | emif.txt | 61 emif1: emif@4c000000 {
62 compatible = "ti,emif-4d";
73 emif: emif@4c000000 {
80 emif1: emif@4c000000 {
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/memory-controllers/ti/ |
| D | emif.txt | 61 emif1: emif@4c000000 {
62 compatible = "ti,emif-4d";
73 emif: emif@4c000000 {
80 emif1: emif@4c000000 {
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | samsung,s3c2412-clock.txt | 32 clocks: clock-controller@4c000000 {
45 interrupts = <1 23 3 4>, <1 23 4 4>;
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| D | samsung,s3c2410-clock.txt | 33 clocks: clock-controller@4c000000 {
46 interrupts = <1 23 3 4>, <1 23 4 4>;
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| D | samsung,s3c2443-clock.txt | 37 clocks: clock-controller@4c000000 {
50 interrupts = <1 23 3 4>, <1 23 4 4>;
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/clock/ |
| D | samsung,s3c2412-clock.txt | 32 clocks: clock-controller@4c000000 {
45 interrupts = <1 23 3 4>, <1 23 4 4>;
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| D | samsung,s3c2410-clock.txt | 33 clocks: clock-controller@4c000000 {
46 interrupts = <1 23 3 4>, <1 23 4 4>;
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| D | samsung,s3c2443-clock.txt | 37 clocks: clock-controller@4c000000 {
50 interrupts = <1 23 3 4>, <1 23 4 4>;
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/hwlock/ |
| D | st,stm32-hwspinlock.yaml | 42 hwspinlock@4c000000 {
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mips/cavium/ |
| D | sata-uctl.txt | 28 uctl@118006c000000 {
40 interrupts = <2 4>; /* Bit: 2, level */
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/mips/cavium/ |
| D | sata-uctl.txt | 28 uctl@118006c000000 {
40 interrupts = <2 4>; /* Bit: 2, level */
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/ |
| D | pxa-usb.txt | 24 usb0: ohci@4c000000 {
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/usb/ |
| D | pxa-usb.txt | 24 usb0: ohci@4c000000 {
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| /kernel/linux/linux-4.19/arch/arm/boot/dts/ |
| D | s3c2416.dtsi | 26 interrupt-controller@4a000000 {
30 clocks: clock-controller@4c000000 {
72 interrupts = <1 18 24 4>, <1 18 25 4>;
80 sdhci_1: sdhci@4ac00000 {
91 sdhci_0: sdhci@4a800000 {
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| D | spear320-evb.dts | 29 st,pinmux-mode = <4>;
89 fsmc: flash@4c000000 {
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| D | pxa27x.dtsi | 27 reg = <0x40e00054 0x20 0x40e0000c 0xc 0x40e0010c 4
38 usb0: usb@4c000000 {
95 interrupts = <4>;
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | s3c2416.dtsi | 31 clocks: clock-controller@4c000000 {
40 interrupts = <1 18 24 4>, <1 18 25 4>;
48 sdhci_1: sdhci@4ac00000 {
59 sdhci_0: sdhci@4a800000 {
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| D | spear320-evb.dts | 23 st,pinmux-mode = <4>;
83 fsmc: flash@4c000000 {
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| D | spear320.dtsi | 32 fsmc: flash@4c000000 {
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| D | pxa27x.dtsi | 27 reg = <0x40e00054 0x20 0x40e0000c 0xc 0x40e0010c 4
38 usb0: usb@4c000000 {
95 interrupts = <4>;
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| D | aspeed-bmc-opp-vesnin.dts | 30 flash_memory: region@5c000000 {
40 gpios = <&gpio ASPEED_GPIO(R, 4) GPIO_ACTIVE_LOW>;
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/interrupt-controller/ |
| D | sifive,plic-1.0.0.txt | 10 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
45 plic: interrupt-controller@c000000 {
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | sifive,plic-1.0.0.yaml | 17 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
84 plic: interrupt-controller@c000000 {
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| /kernel/linux/linux-4.19/arch/sh/mm/ |
| D | Kconfig | 15 On other systems (such as the SH-3 and 4) where an MMU exists,
45 The page size is not necessarily 4KB. Keep this in mind when
58 boards typically map RAM at 0C000000.
92 32-bits through the SH-4A PMB. If this is not set, legacy
172 bool "4kB"
192 This enables support for 64kB pages, possible on all SH-4
215 bool "4MB"
260 Since there's sill some aliasing issues on SH-4, this option will
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| /kernel/linux/linux-5.10/arch/sh/mm/ |
| D | Kconfig | 12 On other systems (such as the SH-3 and 4) where an MMU exists,
41 The page size is not necessarily 4KB. Keep this in mind when
54 boards typically map RAM at 0C000000.
87 32-bits through the SH-4A PMB. If this is not set, legacy
167 bool "4kB"
187 This enables support for 64kB pages, possible on all SH-4
210 bool "4MB"
251 Since there's sill some aliasing issues on SH-4, this option will
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