| /kernel/linux/linux-5.10/drivers/net/wireless/ath/wcn36xx/ |
| D | txrx.c | 58 { 65, 0, RX_ENC_HT, 0, RATE_INFO_BW_20 },
78 { 65, 0, RX_ENC_HT, RX_ENC_FLAG_HT_GF, RATE_INFO_BW_20 },
121 /* 11ac 20 MHz 800ns GI MCS 0-8 */
122 { 65, 0, RX_ENC_HT, 0, RATE_INFO_BW_20 },
143 /* 11ac 20 MHz 400ns SGI MCS 6-8 */
153 /* 11ac 40 MHz 800ns GI MCS 0-9 */
174 /* 11ac 40 MHz 400ns SGI MCS 5-7 */
182 /* 11ac 40 MHz 400ns SGI MCS 5-7 */
189 /* 11ac 80 MHz 800ns GI MCS 0-7 */
202 /* 11ac 80 MHz 800 ns GI MCS 8-9 */
[all …]
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| /kernel/linux/linux-5.10/arch/x86/kernel/cpu/ |
| D | transmeta.c | 27 char cpu_info[65]; in init_transmeta()
39 pr_info("CPU: Processor revision %u.%u.%u.%u, %u MHz\n", in init_transmeta()
50 pr_info("CPU: Processor revision %08X, %u MHz\n", in init_transmeta()
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| /kernel/linux/linux-4.19/arch/x86/kernel/cpu/ |
| D | transmeta.c | 27 char cpu_info[65]; in init_transmeta()
39 pr_info("CPU: Processor revision %u.%u.%u.%u, %u MHz\n", in init_transmeta()
50 pr_info("CPU: Processor revision %08X, %u MHz\n", in init_transmeta()
|
| /kernel/linux/linux-5.10/Documentation/hwmon/ |
| D | adm1021.rst | 119 are possible between -65 and +127 degrees, with a resolution of one degree.
137 era (with 400 MHz FSB) had chips with only one temperature sensor.
150 didn't have these sensors. Next generations of Xeon processors (533 MHz
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| /kernel/linux/linux-4.19/Documentation/hwmon/ |
| D | adm1021 | 79 are possible between -65 and +127 degrees, with a resolution of one degree.
97 era (with 400 MHz FSB) had chips with only one temperature sensor.
110 didn't have these sensors. Next generations of Xeon processors (533 MHz
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| /kernel/linux/linux-4.19/drivers/clk/uniphier/ |
| D | clk-uniphier-sys.c | 92 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
93 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
94 UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
95 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
108 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
109 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
110 UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125), /* 589.824 MHz */
111 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
112 UNIPHIER_CLK_FACTOR("gpll", -1, "ref", 10, 1), /* 250 MHz */
137 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/uniphier/ |
| D | clk-uniphier-sys.c | 83 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
84 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
85 UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
86 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
99 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
100 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 288, 25), /* 288 MHz */
101 UNIPHIER_CLK_FACTOR("a2pll", -1, "upll", 256, 125), /* 589.824 MHz */
102 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
103 UNIPHIER_CLK_FACTOR("gpll", -1, "ref", 10, 1), /* 250 MHz */
128 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 64, 1), /* 1600 MHz */
[all …]
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| /kernel/linux/linux-4.19/drivers/clk/spear/ |
| D | spear1340_clock.c | 167 /* PCLK 24MHz */
168 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
169 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
170 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
171 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
172 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
173 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
175 {.mode = 0, .m = 0x96, .n = 0x06, .p = 0x0}, /* vco 1200, pll 1200 MHz */
180 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
181 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/spear/ |
| D | spear1340_clock.c | 167 /* PCLK 24MHz */
168 {.mode = 0, .m = 0x83, .n = 0x04, .p = 0x5}, /* vco 1572, pll 49.125 MHz */
169 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x3}, /* vco 1000, pll 125 MHz */
170 {.mode = 0, .m = 0x64, .n = 0x06, .p = 0x1}, /* vco 800, pll 400 MHz */
171 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x1}, /* vco 1000, pll 500 MHz */
172 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x1}, /* vco 1328, pll 664 MHz */
173 {.mode = 0, .m = 0xC8, .n = 0x06, .p = 0x1}, /* vco 1600, pll 800 MHz */
175 {.mode = 0, .m = 0x96, .n = 0x06, .p = 0x0}, /* vco 1200, pll 1200 MHz */
180 {.mode = 0, .m = 0x7D, .n = 0x06, .p = 0x2}, /* vco 1000, pll 250 MHz */
181 {.mode = 0, .m = 0xA6, .n = 0x06, .p = 0x2}, /* vco 1328, pll 332 MHz */
[all …]
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| /kernel/linux/linux-5.10/arch/powerpc/boot/dts/ |
| D | mpc5125twr.dts | 39 timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
40 bus-frequency = <198000000>; // 198 MHz csb bus
41 clock-frequency = <396000000>; // 396 MHz ppc core
72 bus-frequency = <66000000>; // 66 MHz ips bus
289 interrupts = <65 0x8>;
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| /kernel/linux/linux-4.19/arch/powerpc/boot/dts/ |
| D | mpc5125twr.dts | 43 timebase-frequency = <49500000>;// 49.5 MHz (csb/4)
44 bus-frequency = <198000000>; // 198 MHz csb bus
45 clock-frequency = <396000000>; // 396 MHz ppc core
76 bus-frequency = <66000000>; // 66 MHz ips bus
293 interrupts = <65 0x8>;
|
| /kernel/linux/linux-5.10/drivers/media/dvb-frontends/ |
| D | mxl5xx_defs.h | 103 MXL_XCPU_PID_FLT_CFG_CMD = 65,
400 MXL_HYDRA_STEP_SIZE_24_XTAL_102_05KHZ, /* 102.05 KHz for 24 MHz XTAL */
401 MXL_HYDRA_STEP_SIZE_24_XTAL_204_10KHZ, /* 204.10 KHz for 24 MHz XTAL */
402 MXL_HYDRA_STEP_SIZE_24_XTAL_306_15KHZ, /* 306.15 KHz for 24 MHz XTAL */
403 MXL_HYDRA_STEP_SIZE_24_XTAL_408_20KHZ, /* 408.20 KHz for 24 MHz XTAL */
405 MXL_HYDRA_STEP_SIZE_27_XTAL_102_05KHZ, /* 102.05 KHz for 27 MHz XTAL */
406 MXL_HYDRA_STEP_SIZE_27_XTAL_204_35KHZ, /* 204.35 KHz for 27 MHz XTAL */
407 MXL_HYDRA_STEP_SIZE_27_XTAL_306_52KHZ, /* 306.52 KHz for 27 MHz XTAL */
408 MXL_HYDRA_STEP_SIZE_27_XTAL_408_69KHZ, /* 408.69 KHz for 27 MHz XTAL */
437 MXL_HYDRA_SEARCH_MAX_OFFSET = 0, /* DMD searches for max freq offset (i.e. 5MHz) */
[all …]
|
| /kernel/linux/linux-4.19/drivers/media/dvb-frontends/ |
| D | mxl5xx_defs.h | 102 MXL_XCPU_PID_FLT_CFG_CMD = 65,
399 MXL_HYDRA_STEP_SIZE_24_XTAL_102_05KHZ, /* 102.05 KHz for 24 MHz XTAL */
400 MXL_HYDRA_STEP_SIZE_24_XTAL_204_10KHZ, /* 204.10 KHz for 24 MHz XTAL */
401 MXL_HYDRA_STEP_SIZE_24_XTAL_306_15KHZ, /* 306.15 KHz for 24 MHz XTAL */
402 MXL_HYDRA_STEP_SIZE_24_XTAL_408_20KHZ, /* 408.20 KHz for 24 MHz XTAL */
404 MXL_HYDRA_STEP_SIZE_27_XTAL_102_05KHZ, /* 102.05 KHz for 27 MHz XTAL */
405 MXL_HYDRA_STEP_SIZE_27_XTAL_204_35KHZ, /* 204.35 KHz for 27 MHz XTAL */
406 MXL_HYDRA_STEP_SIZE_27_XTAL_306_52KHZ, /* 306.52 KHz for 27 MHz XTAL */
407 MXL_HYDRA_STEP_SIZE_27_XTAL_408_69KHZ, /* 408.69 KHz for 27 MHz XTAL */
436 MXL_HYDRA_SEARCH_MAX_OFFSET = 0, /* DMD searches for max freq offset (i.e. 5MHz) */
[all …]
|
| /kernel/linux/linux-4.19/arch/m68k/include/asm/ |
| D | macints.h | 117 #define IRQ_BABOON_1 (65)
124 #define INT_CLK 24576 /* CLK while int_clk =2.456MHz and divide = 100 */
|
| /kernel/linux/linux-5.10/drivers/clk/versatile/ |
| D | clk-icst.c | 107 * 33 or 25 MHz respectively. in vco_get()
262 /* Divides between 3 and 50 MHz in steps of 0.25 MHz */ in icst_round_rate()
267 /* Slam to closest 0.25 MHz */ in icst_round_rate()
273 * If we're below or less than halfway from 25 to 33 MHz in icst_round_rate()
274 * select 25 MHz in icst_round_rate()
415 .rd_max = 65,
438 /* Minimum 12 MHz, VDW = 4 */
441 * Maximum 160 MHz, VDW = 152 for all core modules, but
443 * go to 200 MHz (max VDW = 192).
456 /* Minimum 3 MHz, VDW = 4 */
[all …]
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| /kernel/linux/linux-4.19/drivers/media/tuners/ |
| D | fc0012.c | 226 /* fix for frequency less than 45 MHz */ in fc0012_set_params()
357 -63, -65, -54, -60, in fc0012_get_rf_strength()
360 65, 63, 61, 58, in fc0012_get_rf_strength()
420 .frequency_min_hz = 37 * MHz, /* estimate */
421 .frequency_max_hz = 862 * MHz, /* estimate */
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| /kernel/linux/linux-5.10/drivers/media/tuners/ |
| D | fc0012.c | 217 /* fix for frequency less than 45 MHz */ in fc0012_set_params()
348 -63, -65, -54, -60, in fc0012_get_rf_strength()
351 65, 63, 61, 58, in fc0012_get_rf_strength()
411 .frequency_min_hz = 37 * MHz, /* estimate */
412 .frequency_max_hz = 862 * MHz, /* estimate */
|
| /kernel/linux/linux-5.10/Documentation/fb/ |
| D | viafb.modes | 10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
98 # 640x480, 120 Hz, Non-Interlaced (52.406 MHz dotclock)
[all …]
|
| /kernel/linux/linux-4.19/Documentation/fb/ |
| D | viafb.modes | 10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
98 # 640x480, 120 Hz, Non-Interlaced (52.406 MHz dotclock)
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/gma500/ |
| D | cdv_intel_display.c | 56 /* The single-channel range is 25-112Mhz, and dual-channel
57 * is 80-224Mhz. Prefer single channel as much as possible.
68 .m2 = {.min = 65, .max = 130},
92 .m2 = {.min = 65, .max = 130},
625 /* low-end sku, 96/100 mhz */ in cdv_intel_crtc_mode_set()
628 /* high-end sku, 27/100 mhz */ in cdv_intel_crtc_mode_set()
635 * for DP/eDP. When using SSC clock, the ref clk is 100MHz.Otherwise in cdv_intel_crtc_mode_set()
636 * it will be 27MHz. From the VBIOS code it seems that the pipe A choose in cdv_intel_crtc_mode_set()
637 * 27MHz for DP/eDP while the Pipe B chooses the 100MHz. in cdv_intel_crtc_mode_set()
647 DRM_DEBUG_KMS("Use SSC reference clock %d Mhz\n", dev_priv->lvds_ssc_freq); in cdv_intel_crtc_mode_set()
[all …]
|
| /kernel/linux/linux-4.19/drivers/clk/versatile/ |
| D | clk-icst.c | 122 * 33 or 25 MHz respectively. in vco_get()
277 /* Divides between 3 and 50 MHz in steps of 0.25 MHz */ in icst_round_rate()
282 /* Slam to closest 0.25 MHz */ in icst_round_rate()
288 * If we're below or less than halfway from 25 to 33 MHz in icst_round_rate()
289 * select 25 MHz in icst_round_rate()
429 .rd_max = 65,
452 /* Minimum 12 MHz, VDW = 4 */
455 * Maximum 160 MHz, VDW = 152 for all core modules, but
457 * go to 200 MHz (max VDW = 192).
470 /* Minimum 3 MHz, VDW = 4 */
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/ |
| D | clk-vt8500.c | 380 * Where O1 is 900MHz...3GHz;
381 * O2 is 600MHz >= (M * parent) / P >= 300MHz;
382 * M is 36...120 [25MHz parent]; D is 1 or 2 or 4 or 8.
384 * D = 8: 37,5MHz...75MHz
385 * D = 4: 75MHz...150MHz
386 * D = 2: 150MHz...300MHz
387 * D = 1: 300MHz...600MHz
427 /* calculate frequency (MHz) after pre-divisor */ in wm8750_get_filter()
431 pr_warn("%s: PLL recommended input frequency 10..200Mhz (requested %d Mhz)\n", in wm8750_get_filter()
438 else if (freq >= 65) in wm8750_get_filter()
|
| /kernel/linux/linux-5.10/scripts/ |
| D | extract_xc3028.pl | 590 # Firmware 48, type: SCODE FW HAS IF (0x60000000), IF = 3.28 MHz id: (0000000000000000), size: 192
600 # Firmware 49, type: SCODE FW HAS IF (0x60000000), IF = 3.30 MHz id: (0000000000000000), size: 192
610 # Firmware 50, type: SCODE FW HAS IF (0x60000000), IF = 3.44 MHz id: (0000000000000000), size: 192
620 # Firmware 51, type: SCODE FW HAS IF (0x60000000), IF = 3.46 MHz id: (0000000000000000), size: 192
630 …# Firmware 52, type: SCODE FW DTV6 ATSC OREN36 HAS IF (0x60210020), IF = 3.80 MHz id: (0000000000…
640 # Firmware 53, type: SCODE FW HAS IF (0x60000000), IF = 4.00 MHz id: (0000000000000000), size: 192
650 …# Firmware 54, type: SCODE FW DTV6 ATSC TOYOTA388 HAS IF (0x60410020), IF = 4.08 MHz id: (0000000…
660 # Firmware 55, type: SCODE FW HAS IF (0x60000000), IF = 4.20 MHz id: (0000000000000000), size: 192
670 …# Firmware 56, type: SCODE FW MONO HAS IF (0x60008000), IF = 4.32 MHz id: NTSC/M Kr (000000000000…
680 # Firmware 57, type: SCODE FW HAS IF (0x60000000), IF = 4.45 MHz id: (0000000000000000), size: 192
[all …]
|
| /kernel/linux/linux-4.19/scripts/ |
| D | extract_xc3028.pl | 590 # Firmware 48, type: SCODE FW HAS IF (0x60000000), IF = 3.28 MHz id: (0000000000000000), size: 192
600 # Firmware 49, type: SCODE FW HAS IF (0x60000000), IF = 3.30 MHz id: (0000000000000000), size: 192
610 # Firmware 50, type: SCODE FW HAS IF (0x60000000), IF = 3.44 MHz id: (0000000000000000), size: 192
620 # Firmware 51, type: SCODE FW HAS IF (0x60000000), IF = 3.46 MHz id: (0000000000000000), size: 192
630 …# Firmware 52, type: SCODE FW DTV6 ATSC OREN36 HAS IF (0x60210020), IF = 3.80 MHz id: (0000000000…
640 # Firmware 53, type: SCODE FW HAS IF (0x60000000), IF = 4.00 MHz id: (0000000000000000), size: 192
650 …# Firmware 54, type: SCODE FW DTV6 ATSC TOYOTA388 HAS IF (0x60410020), IF = 4.08 MHz id: (0000000…
660 # Firmware 55, type: SCODE FW HAS IF (0x60000000), IF = 4.20 MHz id: (0000000000000000), size: 192
670 …# Firmware 56, type: SCODE FW MONO HAS IF (0x60008000), IF = 4.32 MHz id: NTSC/M Kr (000000000000…
680 # Firmware 57, type: SCODE FW HAS IF (0x60000000), IF = 4.45 MHz id: (0000000000000000), size: 192
[all …]
|
| /kernel/linux/linux-4.19/drivers/gpu/drm/gma500/ |
| D | cdv_intel_display.c | 66 /* The single-channel range is 25-112Mhz, and dual-channel
67 * is 80-224Mhz. Prefer single channel as much as possible.
78 .m2 = {.min = 65, .max = 130},
102 .m2 = {.min = 65, .max = 130},
638 /* low-end sku, 96/100 mhz */ in cdv_intel_crtc_mode_set()
641 /* high-end sku, 27/100 mhz */ in cdv_intel_crtc_mode_set()
648 * for DP/eDP. When using SSC clock, the ref clk is 100MHz.Otherwise in cdv_intel_crtc_mode_set()
649 * it will be 27MHz. From the VBIOS code it seems that the pipe A choose in cdv_intel_crtc_mode_set()
650 * 27MHz for DP/eDP while the Pipe B chooses the 100MHz. in cdv_intel_crtc_mode_set()
660 DRM_DEBUG_KMS("Use SSC reference clock %d Mhz\n", dev_priv->lvds_ssc_freq); in cdv_intel_crtc_mode_set()
[all …]
|