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/kernel/linux/linux-5.10/drivers/mtd/nand/raw/
Dnand_ids.c1 // SPDX-License-Identifier: GPL-2.0-only
29 {"TC58NVG0S3E 1G 3.3V 8-bit",
31 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
34 SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
37 SZ_4K, SZ_512, SZ_256K, 0, 8, 256, NAND_ECC_INFO(8, SZ_512) },
38 {"TC58NVG3S0F 8G 3.3V 8-bit",
40 SZ_4K, SZ_1K, SZ_256K, 0, 8, 232, NAND_ECC_INFO(4, SZ_512) },
41 {"TC58NVG5D2 32G 3.3V 8-bit",
[all …]
/kernel/linux/linux-4.19/drivers/mtd/nand/raw/
Dnand_ids.c31 {"TC58NVG0S3E 1G 3.3V 8-bit",
33 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512),
35 {"TC58NVG2S0F 4G 3.3V 8-bit",
37 SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },
38 {"TC58NVG2S0H 4G 3.3V 8-bit",
40 SZ_4K, SZ_512, SZ_256K, 0, 8, 256, NAND_ECC_INFO(8, SZ_512) },
41 {"TC58NVG3S0F 8G 3.3V 8-bit",
43 SZ_4K, SZ_1K, SZ_256K, 0, 8, 232, NAND_ECC_INFO(4, SZ_512) },
44 {"TC58NVG5D2 32G 3.3V 8-bit",
46 SZ_8K, SZ_4K, SZ_1M, 0, 8, 640, NAND_ECC_INFO(40, SZ_1K) },
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/
Dtrivial-devices.txt12 abracon,abb5zes3 AB-RTCMC-32.768kHz-B5ZE-S3: Real Time Clock/Calendar Module with I2C Interface
13 ad,ad7414 SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature …
14 ad,adm9240 ADM9240: Complete System Hardware Monitor for uProcessor-Based Systems
15 adi,adt7461 +/-1C TDM Extended Temp Range I.C
16 adt7461 +/-1C TDM Extended Temp Range I.C
17 adi,adt7473 +/-1C TDM Extended Temp Range I.C
18 adi,adt7475 +/-1C TDM Extended Temp Range I.C
19 adi,adt7476 +/-1C TDM Extended Temp Range I.C
20 adi,adt7490 +/-1C TDM Extended Temp Range I.C
21 adi,adxl345 Three-Axis Digital Accelerometer
[all …]
/kernel/linux/linux-4.19/drivers/net/fddi/skfp/h/
Dskfbi.h19 * FDDI-Fx (x := {I(SA), P(CI)})
23 /*--------------------------------------------------------------------------*/
34 #define PCI_VENDOR_ID 0x00 /* 16 bit Vendor ID */
35 #define PCI_DEVICE_ID 0x02 /* 16 bit Device ID */
36 #define PCI_COMMAND 0x04 /* 16 bit Command */
37 #define PCI_STATUS 0x06 /* 16 bit Status */
38 #define PCI_REV_ID 0x08 /* 8 bit Revision ID */
39 #define PCI_CLASS_CODE 0x09 /* 24 bit Class Code */
40 #define PCI_CACHE_LSZ 0x0c /* 8 bit Cache Line Size */
41 #define PCI_LAT_TIM 0x0d /* 8 bit Latency Timer */
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/
Dtrivial-devices.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/trivial-devices.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
28 - enum:
29 … # SMBus/I2C Digital Temperature Sensor in 6-Pin SOT with SMBus Alert and Over Temperature Pin
30 - ad,ad7414
31 # ADM9240: Complete System Hardware Monitor for uProcessor-Based Systems
32 - ad,adm9240
[all …]
/kernel/linux/linux-5.10/drivers/net/fddi/skfp/h/
Dskfbi.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
15 * FDDI-Fx (x := {I(SA), P(CI)})
19 /*--------------------------------------------------------------------------*/
40 #define B0_RAP 0x0000 /* 8 bit register address port */
41 /* 0x0001 - 0x0003: reserved */
42 #define B0_CTRL 0x0004 /* 8 bit control register */
43 #define B0_DAS 0x0005 /* 8 Bit control register (DAS) */
44 #define B0_LED 0x0006 /* 8 Bit LED register */
45 #define B0_TST_CTRL 0x0007 /* 8 bit test control register */
46 #define B0_ISRC 0x0008 /* 32 bit Interrupt source register */
[all …]
/kernel/linux/linux-5.10/include/soc/mscc/
Docelot_dev.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
11 #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7)
12 #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6)
13 #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5)
14 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4)
15 #define DEV_CLOCK_CFG_PORT_RST BIT(3)
16 #define DEV_CLOCK_CFG_PHY_RST BIT(2)
20 #define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4)
21 #define DEV_PORT_MISC_FWD_PAUSE_ENA BIT(3)
22 #define DEV_PORT_MISC_FWD_CTRL_ENA BIT(2)
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/vc4/
Dvc4_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2014-2015 Broadcom
26 ('3' << 8) | \
37 # define V3D_IDENT1_QUPS_MASK VC4_MASK(11, 8)
38 # define V3D_IDENT1_QUPS_SHIFT 8
47 # define V3D_L2CACTL_L2CCLR BIT(2)
48 # define V3D_L2CACTL_L2CDIS BIT(1)
49 # define V3D_L2CACTL_L2CENA BIT(0)
56 # define V3D_SLCACTL_UCC_MASK VC4_MASK(11, 8)
57 # define V3D_SLCACTL_UCC_SHIFT 8
[all …]
/kernel/linux/linux-4.19/drivers/net/ethernet/mscc/
Docelot_dev.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
13 #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7)
14 #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6)
15 #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5)
16 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4)
17 #define DEV_CLOCK_CFG_PORT_RST BIT(3)
18 #define DEV_CLOCK_CFG_PHY_RST BIT(2)
24 #define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4)
25 #define DEV_PORT_MISC_FWD_PAUSE_ENA BIT(3)
26 #define DEV_PORT_MISC_FWD_CTRL_ENA BIT(2)
[all …]
Docelot_dev_gmii.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
13 #define DEV_GMII_PORT_MODE_CLOCK_CFG_MAC_TX_RST BIT(5)
14 #define DEV_GMII_PORT_MODE_CLOCK_CFG_MAC_RX_RST BIT(4)
15 #define DEV_GMII_PORT_MODE_CLOCK_CFG_PORT_RST BIT(3)
16 #define DEV_GMII_PORT_MODE_CLOCK_CFG_PHY_RST BIT(2)
22 #define DEV_GMII_PORT_MODE_PORT_MISC_MPLS_RX_ENA BIT(5)
23 #define DEV_GMII_PORT_MODE_PORT_MISC_FWD_ERROR_ENA BIT(4)
24 #define DEV_GMII_PORT_MODE_PORT_MISC_FWD_PAUSE_ENA BIT(3)
25 #define DEV_GMII_PORT_MODE_PORT_MISC_FWD_CTRL_ENA BIT(2)
26 #define DEV_GMII_PORT_MODE_PORT_MISC_GMII_LOOP_ENA BIT(1)
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/
Dmt76x02_regs.h1 /* SPDX-License-Identifier: ISC */
15 #define MT_CMB_CTRL_XTAL_RDY BIT(22)
16 #define MT_CMB_CTRL_PLL_LD BIT(23)
21 #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
24 #define MT_EFUSE_CTRL_KICK BIT(30)
25 #define MT_EFUSE_CTRL_SEL BIT(31)
31 #define MT_COEXCFG0_COEX_EN BIT(0)
34 #define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0)
35 #define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1)
36 #define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2)
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt7601u/
Dregs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
18 #define MT_CMB_CTRL_XTAL_RDY BIT(22)
19 #define MT_CMB_CTRL_PLL_LD BIT(23)
24 #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
27 #define MT_EFUSE_CTRL_KICK BIT(30)
28 #define MT_EFUSE_CTRL_SEL BIT(31)
34 #define MT_COEXCFG0_COEX_EN BIT(0)
37 #define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0)
38 #define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1)
39 #define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2)
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/vc4/
Dvc4_regs.h2 * Copyright © 2014-2015 Broadcom
30 ('3' << 8) | \
41 # define V3D_IDENT1_QUPS_MASK VC4_MASK(11, 8)
42 # define V3D_IDENT1_QUPS_SHIFT 8
51 # define V3D_L2CACTL_L2CCLR BIT(2)
52 # define V3D_L2CACTL_L2CDIS BIT(1)
53 # define V3D_L2CACTL_L2CENA BIT(0)
60 # define V3D_SLCACTL_UCC_MASK VC4_MASK(11, 8)
61 # define V3D_SLCACTL_UCC_SHIFT 8
68 # define V3D_INT_SPILLUSE BIT(3)
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/mt7603/
Dregs.h1 /* SPDX-License-Identifier: ISC */
28 #define MT_INT_RX_DONE(_n) BIT(_n)
31 #define MT_INT_TX_DONE(_n) BIT((_n) + 4)
33 #define MT_INT_RX_COHERENT BIT(20)
34 #define MT_INT_TX_COHERENT BIT(21)
35 #define MT_INT_MAC_IRQ3 BIT(27)
37 #define MT_INT_MCU_CMD BIT(30)
40 #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)
41 #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1)
42 #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2)
[all …]
/kernel/linux/linux-4.19/drivers/net/ethernet/marvell/
Dskge.h1 /* SPDX-License-Identifier: GPL-2.0 */
137 /* B0_CTST 16 bit Control/Status register */
139 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
140 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
141 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
144 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
148 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
154 /* B0_LED 8 Bit LED register */
155 /* Bit 7.. 2: reserved */
159 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/marvell/
Dskge.h1 /* SPDX-License-Identifier: GPL-2.0 */
131 /* B0_CTST 16 bit Control/Status register */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
138 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
142 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
148 /* B0_LED 8 Bit LED register */
149 /* Bit 7.. 2: reserved */
153 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/intel/ice/
Dice_hw_autogen.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 /* Machine-generated file */
19 #define PF_FW_ARQLEN_ARQVFE_M BIT(28)
20 #define PF_FW_ARQLEN_ARQOVFL_M BIT(29)
21 #define PF_FW_ARQLEN_ARQCRIT_M BIT(30)
22 #define PF_FW_ARQLEN_ARQENABLE_M BIT(31)
30 #define PF_FW_ATQLEN_ATQVFE_M BIT(28)
31 #define PF_FW_ATQLEN_ATQOVFL_M BIT(29)
32 #define PF_FW_ATQLEN_ATQCRIT_M BIT(30)
35 #define PF_FW_ATQLEN_ATQENABLE_M BIT(31)
[all …]
/kernel/linux/linux-5.10/drivers/media/platform/vsp1/
Dvsp1_regs.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * vsp1_regs.h -- R-Car VSP1 Registers Definitions
13 /* -----------------------------------------------------------------------------
18 #define VI6_CMD_UPDHDR BIT(4)
19 #define VI6_CMD_STRCMD BIT(0)
22 #define VI6_CLK_DCSWT_CSTPW_MASK (0xff << 8)
23 #define VI6_CLK_DCSWT_CSTPW_SHIFT 8
28 #define VI6_SRESET_SRTS(n) BIT(n)
31 #define VI6_STATUS_FLD_STD(n) BIT((n) + 28)
32 #define VI6_STATUS_SYS_ACT(n) BIT((n) + 8)
[all …]
/kernel/linux/linux-5.10/drivers/gpio/
Dgpio-ws16c48.c1 // SPDX-License-Identifier: GPL-2.0-only
34 * struct ws16c48_gpio - GPIO device private data structure
36 * @io_state: bit I/O state (whether bit is set to input or output)
56 const unsigned port = offset / 8; in ws16c48_gpio_get_direction()
57 const unsigned mask = BIT(offset % 8); in ws16c48_gpio_get_direction()
59 if (ws16c48gpio->io_state[port] & mask) in ws16c48_gpio_get_direction()
68 const unsigned port = offset / 8; in ws16c48_gpio_direction_input()
69 const unsigned mask = BIT(offset % 8); in ws16c48_gpio_direction_input()
72 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); in ws16c48_gpio_direction_input()
74 ws16c48gpio->io_state[port] |= mask; in ws16c48_gpio_direction_input()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/v3d/
Dv3d_regs.h1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2017-2018 Broadcom */
30 # define V3D_HUB_IDENT1_WITH_MSO BIT(19)
31 # define V3D_HUB_IDENT1_WITH_TSY BIT(18)
32 # define V3D_HUB_IDENT1_WITH_TFU BIT(17)
33 # define V3D_HUB_IDENT1_WITH_L3C BIT(16)
36 # define V3D_HUB_IDENT1_NCORES_MASK V3D_MASK(11, 8)
37 # define V3D_HUB_IDENT1_NCORES_SHIFT 8
44 # define V3D_HUB_IDENT2_WITH_MMU BIT(8)
49 # define V3D_HUB_IDENT3_IPREV_MASK V3D_MASK(15, 8)
[all …]
/kernel/linux/linux-5.10/drivers/media/cec/platform/tegra/
Dtegra_cec.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright (c) 2012-2015, NVIDIA CORPORATION. All rights reserved.
11 * Copyright 2016-2017 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
37 #define TEGRA_CEC_HWCTRL_RX_SNOOP BIT(15)
38 #define TEGRA_CEC_HWCTRL_RX_NAK_MODE BIT(16)
39 #define TEGRA_CEC_HWCTRL_TX_NAK_MODE BIT(24)
40 #define TEGRA_CEC_HWCTRL_FAST_SIM_MODE BIT(30)
41 #define TEGRA_CEC_HWCTRL_TX_RX_MODE BIT(31)
43 #define TEGRA_CEC_INPUT_FILTER_MODE BIT(31)
47 #define TEGRA_CEC_TX_REG_EOM BIT(8)
[all …]
/kernel/linux/linux-4.19/drivers/gpio/
Dgpio-ws16c48.c42 * struct ws16c48_gpio - GPIO device private data structure
44 * @io_state: bit I/O state (whether bit is set to input or output)
64 const unsigned port = offset / 8; in ws16c48_gpio_get_direction()
65 const unsigned mask = BIT(offset % 8); in ws16c48_gpio_get_direction()
67 return !!(ws16c48gpio->io_state[port] & mask); in ws16c48_gpio_get_direction()
73 const unsigned port = offset / 8; in ws16c48_gpio_direction_input()
74 const unsigned mask = BIT(offset % 8); in ws16c48_gpio_direction_input()
77 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags); in ws16c48_gpio_direction_input()
79 ws16c48gpio->io_state[port] |= mask; in ws16c48_gpio_direction_input()
80 ws16c48gpio->out_state[port] &= ~mask; in ws16c48_gpio_direction_input()
[all …]
/kernel/linux/linux-4.19/drivers/net/ethernet/intel/ice/
Dice_hw_autogen.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 /* Machine-generated file */
19 #define PF_FW_ARQLEN_ARQVFE_M BIT(PF_FW_ARQLEN_ARQVFE_S)
21 #define PF_FW_ARQLEN_ARQOVFL_M BIT(PF_FW_ARQLEN_ARQOVFL_S)
23 #define PF_FW_ARQLEN_ARQCRIT_M BIT(PF_FW_ARQLEN_ARQCRIT_S)
25 #define PF_FW_ARQLEN_ARQENABLE_M BIT(PF_FW_ARQLEN_ARQENABLE_S)
36 #define PF_FW_ATQLEN_ATQVFE_M BIT(PF_FW_ATQLEN_ATQVFE_S)
38 #define PF_FW_ATQLEN_ATQOVFL_M BIT(PF_FW_ATQLEN_ATQOVFL_S)
40 #define PF_FW_ATQLEN_ATQCRIT_M BIT(PF_FW_ATQLEN_ATQCRIT_S)
42 #define PF_FW_ATQLEN_ATQENABLE_M BIT(PF_FW_ATQLEN_ATQENABLE_S)
[all …]
/kernel/linux/linux-4.19/drivers/net/wireless/mediatek/mt7601u/
Dregs.h26 #define MT_CMB_CTRL_XTAL_RDY BIT(22)
27 #define MT_CMB_CTRL_PLL_LD BIT(23)
32 #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
35 #define MT_EFUSE_CTRL_KICK BIT(30)
36 #define MT_EFUSE_CTRL_SEL BIT(31)
42 #define MT_COEXCFG0_COEX_EN BIT(0)
45 #define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0)
46 #define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1)
47 #define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2)
49 #define MT_WLAN_FUN_CTRL_WLAN_RESET BIT(3) /* MT76x0 */
[all …]
/kernel/linux/linux-5.10/Documentation/gpu/
Dafbc.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 It provides fine-grained random access and minimizes the amount of
21 AFBC streams can contain several components - where a component
37 reside in the least-significant bits of the corresponding linear
42 * Component 0: R(8)
43 * Component 1: G(8)
44 * Component 2: B(8)
45 * Component 3: A(8)
49 * Component 0: R(8)
50 * Component 1: G(8)
[all …]

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