| /kernel/linux/linux-5.10/drivers/bus/ |
| D | bt1-axi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * Baikal-T1 AXI-bus driver
35 * struct bt1_axi - Baikal-T1 AXI-bus private data
37 * @qos_regs: AXI Interconnect QoS tuning registers.
38 * @sys_regs: Baikal-T1 System Controller registers map.
40 * @aclk: AXI reference clock.
41 * @arst: AXI Interconnect reset line.
60 struct bt1_axi *axi = data; in bt1_axi_isr() local
63 regmap_read(axi->sys_regs, BT1_AXI_WERRL, &low); in bt1_axi_isr()
64 regmap_read(axi->sys_regs, BT1_AXI_WERRH, &high); in bt1_axi_isr()
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| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 # Bus Devices
6 menu "Bus devices"
24 bool "ARM Integrator Logic Module bus"
29 Say y here to enable support for the ARM Logic Module bus
33 bool "Broadcom STB GISB bus arbiter"
37 Driver for the Broadcom Set Top Box System-on-a-chip internal bus
39 and internal bus master decoding.
42 bool "Baikal-T1 APB-bus driver"
46 Baikal-T1 AXI-APB bridge is used to access the SoC subsystem CSRs.
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/bus/ |
| D | baikal,bt1-axi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/bus/baikal,bt1-axi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 AXI-bus
11 - Serge Semin <fancer.lancer@gmail.com>
14 AXI3-bus is the main communication bus of Baikal-T1 SoC connecting all
15 high-speed peripheral IP-cores with RAM controller and with MIPS P5600
16 cores. Traffic arbitration is done by means of DW AXI Interconnect (so
17 called AXI Main Interconnect) routing IO requests from one block to
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| D | brcm,bus-axi.txt | 1 Driver for ARM AXI Bus with Broadcom Plugins (bcma)
5 - compatible : brcm,bus-axi
7 - reg : iomem address range of chipcommon core
9 The cores on the AXI bus are automatically detected by bcma with the
13 them manually through device tree. Use an interrupt-map to specify the
14 IRQ used by the devices on the bus. The first address is just an index,
17 The top-level axi bus may contain children representing attached cores
24 axi@18000000 {
25 compatible = "brcm,bus-axi";
28 #address-cells = <1>;
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/dma/ |
| D | adi,axi-dmac.txt | 1 Analog Devices AXI-DMAC DMA controller
4 - compatible: Must be "adi,axi-dmac-1.00.a".
5 - reg: Specification for the controllers memory mapped register map.
6 - interrupts: Specification for the controllers interrupt.
7 - clocks: Phandle and specifier to the controllers AXI interface clock
8 - #dma-cells: Must be 1.
10 Required sub-nodes:
11 - adi,channels: This sub-node must contain a sub-node for each DMA channel. For
12 the channel sub-nodes the following bindings apply. They must match the
15 Required properties for adi,channels sub-node:
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/dma/ |
| D | adi,axi-dmac.txt | 1 Analog Device AXI-DMAC DMA controller
4 - compatible: Must be "adi,axi-dmac-1.00.a".
5 - reg: Specification for the controllers memory mapped register map.
6 - interrupts: Specification for the controllers interrupt.
7 - clocks: Phandle and specifier to the controllers AXI interface clock
8 - #dma-cells: Must be 1.
10 Required sub-nodes:
11 - adi,channels: This sub-node must contain a sub-node for each DMA channel. For
12 the channel sub-nodes the following bindings apply. They must match the
15 Required properties for adi,channels sub-node:
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/bus/ |
| D | brcm,bus-axi.txt | 1 Driver for ARM AXI Bus with Broadcom Plugins (bcma)
5 - compatible : brcm,bus-axi
7 - reg : iomem address range of chipcommon core
9 The cores on the AXI bus are automatically detected by bcma with the
13 them manually through device tree. Use an interrupt-map to specify the
14 IRQ used by the devices on the bus. The first address is just an index,
17 The top-level axi bus may contain children representing attached cores
24 axi@18000000 {
25 compatible = "brcm,bus-axi";
28 #address-cells = <1>;
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | baikal,bt1-ccu-div.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit Dividers
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
22 registers. Baikal-T1 CCU is logically divided into the next components:
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/ |
| D | xilinx_axienet.txt | 1 XILINX AXI ETHERNET Device Tree Bindings
2 --------------------------------------------------------
4 Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
10 Management configuration is done through the AXI interface, while payload is
11 sent and received through means of an AXI DMA controller. This driver
12 includes the DMA driver code, so this driver is incompatible with AXI DMA
18 - compatible : Must be one of "xlnx,axi-ethernet-1.00.a",
19 "xlnx,axi-ethernet-1.01.a", "xlnx,axi-ethernet-2.01.a"
20 - reg : Address and length of the IO space, as well as the address
21 and length of the AXI DMA controller IO space, unless
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| D | snps,dwc-qos-ethernet.txt | 7 IP block. The IP supports multiple options for bus type, clocking and reset
13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
24 same order. See ../clock/clock-bindings.txt.
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/pci/ |
| D | xilinx-pcie.txt | 1 * Xilinx AXI PCIe Root Port Bridge DT description
4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
8 - compatible: Should contain "xlnx,axi-pcie-host-1.00.a"
9 - reg: Should contain AXI PCIe registers location and length
10 - device_type: must be "pci"
11 - interrupts: Should contain AXI PCIe interrupt
12 - interrupt-map-mask,
13 interrupt-map: standard PCI properties to define the mapping of the
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| D | qcom,pcie.txt | 3 - compatible:
7 - "qcom,pcie-ipq8064" for ipq8064
8 - "qcom,pcie-apq8064" for apq8064
9 - "qcom,pcie-apq8084" for apq8084
10 - "qcom,pcie-msm8996" for msm8996 or apq8096
11 - "qcom,pcie-ipq4019" for ipq4019
12 - "qcom,pcie-ipq8074" for ipq8074
14 - reg:
16 Value type: <prop-encoded-array>
17 Definition: Register ranges as listed in the reg-names property
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| D | arm,juno-r1-pcie.txt | 3 This PCIe host controller is based on PLDA XpressRICH3-AXI IP
4 and thus inherits all the common properties defined in plda,xpressrich3-axi.txt
5 as well as the base properties defined in host-generic-pci.txt.
8 - compatible: "arm,juno-r1-pcie"
9 - dma-coherent: The host controller bridges the AXI transactions into PCIe bus
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | xilinx-pcie.txt | 1 * Xilinx AXI PCIe Root Port Bridge DT description
4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
8 - compatible: Should contain "xlnx,axi-pcie-host-1.00.a"
9 - reg: Should contain AXI PCIe registers location and length
10 - device_type: must be "pci"
11 - interrupts: Should contain AXI PCIe interrupt
12 - interrupt-map-mask,
13 interrupt-map: standard PCI properties to define the mapping of the
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| D | qcom,pcie.txt | 3 - compatible:
7 - "qcom,pcie-ipq8064" for ipq8064
8 - "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065
9 - "qcom,pcie-apq8064" for apq8064
10 - "qcom,pcie-apq8084" for apq8084
11 - "qcom,pcie-msm8996" for msm8996 or apq8096
12 - "qcom,pcie-ipq4019" for ipq4019
13 - "qcom,pcie-ipq8074" for ipq8074
14 - "qcom,pcie-qcs404" for qcs404
15 - "qcom,pcie-sdm845" for sdm845
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/net/ |
| D | snps,dwc-qos-ethernet.txt | 7 IP block. The IP supports multiple options for bus type, clocking and reset
13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
24 same order. See ../clock/clock-bindings.txt.
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| /kernel/linux/linux-5.10/Documentation/admin-guide/perf/ |
| D | imx-ddr.rst | 17 (AXI filtering) fields of the perf_event_attr structure, see /sys/bus/event_source/
19 hardware supported that can be used with perf tool, see /sys/bus/event_source/
21 in DDR PMU, see /sys/bus/events_source/devices/imx8_ddr0/caps/.
23 .. code-block:: bash
25 perf stat -a -e imx8_ddr0/cycles/ cmd
26 perf stat -a -e imx8_ddr0/read/,imx8_ddr0/write/ cmd
28 AXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write)
32 indicates whether PMU supports AXI ID filter or not; enhanced_filter indicates
33 whether PMU supports enhanced AXI ID filter or not. Value 0 for un-supported, and
38 --AXI_ID defines AxID matching value.
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/ |
| D | marvell,mmp2-ccic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/marvell,mmp2-ccic.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Lubomir Rintel <lkundrak@v3.sk>
15 pattern: '^camera@[a-f0-9]+$'
18 const: marvell,mmp2-ccic
36 # Documentation/devicetree/bindings/media/video-interfaces.txt
38 remote-endpoint: true
39 hsync-active: true
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| /kernel/linux/linux-4.19/drivers/pci/controller/ |
| D | pcie-cadence.h | 1 // SPDX-License-Identifier: GPL-2.0
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
36 /* Endpoint Bus and Device Number Register */
109 /* Region r Outbound AXI to PCIe Address Translation Register 0 */
114 (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK)
119 #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \ argument
120 (((bus) << 20) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK)
122 /* Region r Outbound AXI to PCIe Address Translation Register 1 */
146 #define CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus) \ argument
147 ((bus) & CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK)
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| /kernel/linux/linux-5.10/drivers/net/ethernet/xilinx/ |
| D | xilinx_axienet.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Definitions for Xilinx Axi Ethernet device driver.
6 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
72 /* Axi DMA Register definitions */
144 /* Axi Ethernet registers definition */
147 #define XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/
179 /* Bit Masks for Axi Ethernet RAF register */
198 /* Bit Masks for Axi Ethernet TPF and IFGP registers */
200 /* Transmit inter-frame gap adjustment value */
203 /* Bit Masks for Axi Ethernet IS, IE and IP registers, Same masks apply
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/ |
| D | marvell,xenon-sdhci.txt | 11 - compatible: should be one of the following
12 - "marvell,armada-3700-sdhci": For controllers on Armada-3700 SoC.
13 Must provide a second register area and marvell,pad-type.
14 - "marvell,armada-ap806-sdhci": For controllers on Armada AP806.
15 - "marvell,armada-cp110-sdhci": For controllers on Armada CP110.
17 - clocks:
20 CP110, the AXI clock is also mandatory.
22 - clock-names:
25 The input clock for the AXI bus must be named as "axi".
27 - reg:
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/mmc/ |
| D | marvell,xenon-sdhci.txt | 11 - compatible: should be one of the following
12 - "marvell,armada-3700-sdhci": For controllers on Armada-3700 SoC.
13 Must provide a second register area and marvell,pad-type.
14 - "marvell,armada-ap806-sdhci": For controllers on Armada AP806.
15 - "marvell,armada-cp110-sdhci": For controllers on Armada CP110.
17 - clocks:
20 CP110, the AXI clock is also mandatory.
22 - clock-names:
25 The input clock for the AXI bus must be named as "axi".
27 - reg:
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| /kernel/linux/linux-5.10/drivers/pci/controller/cadence/ |
| D | pcie-cadence.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
41 /* Endpoint Bus and Device Number Register */
108 (((aperture) - 2) << ((bar) * 8))
129 /* Region r Outbound AXI to PCIe Address Translation Register 0 */
134 (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK)
139 #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \ argument
140 (((bus) << 20) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK)
142 /* Region r Outbound AXI to PCIe Address Translation Register 1 */
166 #define CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus) \ argument
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/ |
| D | microchip,sparx5.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <lars.povlsen@microchip.com>
13 The Microchip Sparx5 SoC is a ARMv8-based used in a family of
14 gigabit TSN-capable gigabit switches.
16 The SparX-5 Ethernet switch family provides a rich set of switching
17 features such as advanced TCAM-based VLAN and QoS processing
19 TCAM-based frame processing using versatile content aware processor
27 - description: The Sparx5 pcb125 board is a modular board,
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| /kernel/linux/linux-4.19/drivers/net/ethernet/xilinx/ |
| D | xilinx_axienet.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Definitions for Xilinx Axi Ethernet device driver.
6 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
71 /* Axi DMA Register definitions */
141 /* Axi Ethernet registers definition */
144 #define XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/
182 /* Bit Masks for Axi Ethernet RAF register */
201 /* Bit Masks for Axi Ethernet TPF and IFGP registers */
203 /* Transmit inter-frame gap adjustment value */
206 /* Bit Masks for Axi Ethernet IS, IE and IP registers, Same masks apply
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