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/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/cascadelakex/
D	other.json	11 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … 24 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … 37 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … 50 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … 63 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … 76 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … 89 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … 102 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … 115 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … 128 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … [all …]
D	memory.json	11 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … 24 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … 37 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … 51 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … 65 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … 79 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … 84 …"BriefDescription": "Counts L1 data cache hardware prefetch requests and software prefetch request… 92 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … 106 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … 120 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … [all …]
D	cache.json	12 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … 26 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … 40 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … 54 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … 78 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … 92 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … 118 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … 132 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … 166 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … 180 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … [all …]
/kernel/linux/linux-5.10/drivers/edac/
D	Kconfig	4 # Licensed and distributed under the GPL 13 tristate "EDAC (Error Detection And Correction) reporting" 40 levels are 0-4 (from low to high) and by default it is set to 2. 68 It should be noticed that keeping both GHES and a hardware-driven 81 Support for error detection and correction of DRAM ECC errors on 88 Recent Opterons (Family 10h and later) provide for Memory Error 90 allows the operator/user to inject Uncorrectable and Correctable 100 In addition, there are two control files, inject_read and inject_write, 101 which trigger the DRAM ECC Read and Write respectively. 107 Support for error detection and correction for Amazon's Annapurna [all …]
/kernel/linux/linux-4.19/tools/perf/pmu-events/arch/x86/skylakex/
D	cache.json	168 …e). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and har… 178 …e). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and har… 188 …and gets hit at least once by demand. The valid outstanding interval is defined until the FB deall… 230 …: "Counts L1D data line replacements including opportunistic replacements, and replacements that r… 240 …ction is considered to be in the Offcore outstanding state between L2 miss and transaction complet… 251 …ction is considered to be in the Offcore outstanding state between L2 miss and transaction complet… 292 …ction is considered to be in the Offcore outstanding state between L2 miss and transaction complet… 313 …ction is considered to be in the Offcore outstanding state between L2 miss and transaction complet… 324 …ction is considered to be in the Offcore outstanding state between L2 miss and transaction complet… 341 "BriefDescription": "Cacheable and noncachaeble code read requests", [all …]
D	memory.json	44 …actional execution aborted due to XRELEASE lock not satisfying the address and value requirements … 47 …: "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", 224 … an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 242 …umber of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly … 301 …es an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", 304 …s an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", 468 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … 476 …"BriefDescription": "Counts demand data reads that miss the L3 and clean or shared data is transfe… 481 …and clean or shared data is transferred from remote cache. Offcore response can be programmed only… 489 …"BriefDescription": "Counts demand data reads that miss the L3 and the modified data is transferre… [all …]
/kernel/linux/linux-4.19/tools/perf/pmu-events/arch/x86/broadwell/
D	memory.json	63 …: "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", 69 …": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch", 188 … an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 222 …"PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subev… 269 …es an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", 279 … an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).", 303 …"PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subev… 433 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … 446 …and the target was non-DRAM system address. Offcore response can be programmed only with a specifi… 454 …"BriefDescription": "Counts demand data reads that hit in the L3 and the target was non-DRAM syste… [all …]
D	cache.json	165 …t level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and in… 175 …t level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and in… 185 …and gets hit at least once by demand. The valid outstanding interval is defined until the FB deall… 227 …nt counts L1D data line replacements including opportunistic replacements, and replacements that r… 237 …ction is considered to be in the Offcore outstanding state between L2 miss and transaction complet… 248 …ction is considered to be in the Offcore outstanding state between L2 miss and transaction complet… 282 …ction is considered to be in the Offcore outstanding state between L2 miss and transaction complet… 305 …ction is considered to be in the Offcore outstanding state between L2 miss and transaction complet… 316 …ction is considered to be in the Offcore outstanding state between L2 miss and transaction complet… 348 … "PublicDescription": "This event counts both cacheable and noncachaeble code read requests.", [all …]
/kernel/linux/linux-5.10/tools/perf/pmu-events/arch/x86/skylakex/
D	memory.json	3 …"BriefDescription": "Counts all demand & prefetch RFOs that miss the L3 and the data is returned f… 11 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … 24 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … 39 …"BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that miss the L3 and the dat… 47 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … 60 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … 65 …"BriefDescription": "Counts all demand data writes (RFOs) that miss the L3 and the modified data i… 73 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … 87 …"BriefDescription": "Counts all prefetch data reads that miss the L3 and the data is returned from… 95 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … [all …]
D	cache.json	3 …"BriefDescription": "Counts all demand code reads that hit in the L3 and sibling core snoops are n… 11 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … 34 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … 67 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … 104 …efetch requests and software prefetch requests that hit in the L3 and the snoop to one of the sibl… 112 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … 117 …nts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line i… 125 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … 138 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … 194 …ogrammed only with a specific pair of event select and counter MSR, and with specific event codes … [all …]
/kernel/linux/linux-4.19/drivers/edac/
D	Kconfig	4 # Licensed and distributed under the GPL 13 tristate "EDAC (Error Detection And Correction) reporting" 40 levels are 0-4 (from low to high) and by default it is set to 2. 68 It should be noticed that keeping both GHES and a hardware-driven 81 Support for error detection and correction of DRAM ECC errors on 88 Recent Opterons (Family 10h and later) provide for Memory Error 90 allows the operator/user to inject Uncorrectable and Correctable 100 In addition, there are two control files, inject_read and inject_write, 101 which trigger the DRAM ECC Read and Write respectively. 107 Support for error detection and correction on the AMD 76x [all …]
/kernel/linux/linux-4.19/Documentation/timers/
D	hrtimers.txt	9 back and forth trying to integrate high-resolution and high-precision 10 features into the existing timer framework, and after testing various 14 to solve this'), and spent a considerable effort trying to integrate 18 - the forced handling of low-resolution and high-resolution timers in 19 the same way leads to a lot of compromises, macro magic and #ifdef 20 mess. The timers.c code is very "tightly coded" around jiffies and 21 32-bitness assumptions, and has been honed and micro-optimized for a 23 for many years - and thus even small extensions to it easily break 25 code is very good and tight code, there's zero problems with it in its 45 error conditions in various I/O paths, such as networking and block [all …]
/kernel/linux/linux-4.19/tools/perf/pmu-events/arch/x86/goldmont/
D	memory.json	26 …s due to memory ordering issues. This occurs when a snoop request happens and the machine is unce… 36 …and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache and targets non-D… 44 …n": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that m… 49 …etch) that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] t… 57 …ds for ownership (RFO) requests (demand & prefetch) that miss the L2 cache and targets non-DRAM sy… 62 …etch) that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] t… 70 …"BriefDescription": "Counts data reads (demand & prefetch) that miss the L2 cache and targets non-… 75 …chers that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] t… 83 …Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache and targets non-DRAM sy… 88 …ystem that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] t… [all …]
/kernel/linux/linux-4.19/Documentation/filesystems/pohmelfs/
D	design_notes.txt	7 POHMELFS first began as a network filesystem with coherent local data and 11 * Locally coherent cache for data and metadata with (potentially) byte-range locks. 13 is very simple and does not use byte-ranges, although they are sent in 15 * Completely async processing of all events except creation of hard and symbolic 16 links, and rename events. 17 Object creation and data reading and writing are processed asynchronously. 19 Ability to create long paths to objects and remove arbitrarily huge 23 * Fast and scalable multithreaded userspace server. Being in userspace it works 24 with any underlying filesystem and still is much faster than async in-kernel NFS one. 26 automatically reconnects to second and so on). [all …]
/kernel/linux/linux-5.10/drivers/pinctrl/intel/
D	Kconfig	12 platforms. Supports 3 banks with 102, 28 and 44 gpios. 19 tristate "Intel Cherryview/Braswell pinctrl and GPIO driver" 24 allows configuring of SoC pins and using them as GPIOs. 27 tristate "Intel Lynxpoint pinctrl and GPIO driver" 36 provides an interface that allows configuring of PCH pins and 47 interface that allows configuring of SoC pins and using them as 59 tristate "Intel Broxton pinctrl and GPIO driver" 64 configuring of SoC pins and using them as GPIOs. 67 tristate "Intel Cannon Lake PCH pinctrl and GPIO driver" 72 of Intel Cannon Lake PCH pins and using them as GPIOs. [all …]
/kernel/linux/linux-4.19/Documentation/media/uapi/v4l/
D	v4l2.rst	39 Revision and Copyright 50 - Documented libv4l, designed and added v4l2grab example, Remote Controller chapter. 54 - Original author of the V4L2 API and documentation. 58 - Original author of the V4L2 API and documentation. 66 - Designed and documented the multi-planar API. 74 - Introduce HSV formats and other minor changes. 78 - Designed and documented the VIDIOC_ENUM_FRAMESIZES and VIDIOC_ENUM_FRAMEINTERVALS ioctls. 86 …ned and documented the VIDIOC_LOG_STATUS ioctl, the extended control ioctls, major parts of the sl… 91 part can be used and distributed without restrictions. 105 ctrl_class and which. Which is used to select the current value of the [all …]
D	hist-v4l2.rst	11 and began to work on documentation, example drivers and applications. 14 another four years and two stable kernel releases until the new API was 28 meaningless ``O_TRUNC`` :ref:`open() <func-open>` flag, and the 29 aliases ``O_NONCAP`` and ``O_NOIO`` were defined. Applications can set 32 identifiers are now ordinals instead of flags, and the 33 ``video_std_construct()`` helper function takes id and 40 struct ``video_standard`` and the color subcarrier fields were 53 and ``V4L2_PIX_FMT_RGB32`` changed to ``V4L2_PIX_FMT_BGR32``. Audio 55 :ref:`VIDIOC_G_CTRL <VIDIOC_G_CTRL>` and 59 module. The ``YUV422`` and ``YUV411`` planar image formats were added. [all …]
/kernel/linux/linux-5.10/Documentation/timers/
D	hrtimers.rst	9 back and forth trying to integrate high-resolution and high-precision 10 features into the existing timer framework, and after testing various 14 to solve this'), and spent a considerable effort trying to integrate 18 - the forced handling of low-resolution and high-resolution timers in 19 the same way leads to a lot of compromises, macro magic and #ifdef 20 mess. The timers.c code is very "tightly coded" around jiffies and 21 32-bitness assumptions, and has been honed and micro-optimized for a 23 for many years - and thus even small extensions to it easily break 25 code is very good and tight code, there's zero problems with it in its 45 error conditions in various I/O paths, such as networking and block [all …]
/kernel/linux/linux-5.10/Documentation/userspace-api/media/v4l/
D	hist-v4l2.rst	12 and began to work on documentation, example drivers and applications. 15 another four years and two stable kernel releases until the new API was 28 meaningless ``O_TRUNC`` :c:func:`open()` flag, and the 29 aliases ``O_NONCAP`` and ``O_NOIO`` were defined. Applications can set 32 identifiers are now ordinals instead of flags, and the 33 ``video_std_construct()`` helper function takes id and 40 struct ``video_standard`` and the color subcarrier fields were 53 and ``V4L2_PIX_FMT_RGB32`` changed to ``V4L2_PIX_FMT_BGR32``. Audio 55 :ref:`VIDIOC_G_CTRL <VIDIOC_G_CTRL>` and 59 module. The ``YUV422`` and ``YUV411`` planar image formats were added. [all …]
/kernel/linux/linux-4.19/drivers/hwmon/
D	Kconfig	13 sensors and various additional features such as the ability to 15 should say Y here and also to the specific driver(s) for your 35 a problem with I2C support and want to see more of what is going 46 AB8500 die and two GPADC channels. The GPADC channel are preferably 57 and second revision of the Abit uGuru chip. The voltage and frequency 60 Abit motherboards from before end 2005). For more info and a list 73 and their settings is supported. The third revision of the Abit 75 2005). For more info and a list of which motherboards have which 82 tristate "Analog Devices AD7314 and compatibles" 86 AD7314, ADT7301 and ADT7302 temperature sensors. [all …]
/kernel/linux/linux-4.19/Documentation/core-api/
D	workqueue.rst	14 is needed and the workqueue (wq) API is the most commonly used 20 queue is called workqueue and the thread is called worker. 32 worker thread per CPU and a single threaded (ST) wq had one worker 35 wq users over the years and with the number of CPU cores continuously 40 provided was unsatisfactory. The limitation was common to both ST and 47 The tension between the provided level of concurrency and resource 49 choosing to use ST wq for polling PIOs and accepting an unnecessary 64 * Automatically regulate worker pool and level of concurrency so that 77 item pointing to that function and queue that work item on a 86 subsystems and drivers queue work items on and the backend mechanism [all …]
/kernel/linux/linux-5.10/Documentation/core-api/
D	workqueue.rst	14 is needed and the workqueue (wq) API is the most commonly used 20 queue is called workqueue and the thread is called worker. 32 worker thread per CPU and a single threaded (ST) wq had one worker 35 wq users over the years and with the number of CPU cores continuously 40 provided was unsatisfactory. The limitation was common to both ST and 47 The tension between the provided level of concurrency and resource 49 choosing to use ST wq for polling PIOs and accepting an unnecessary 64 * Automatically regulate worker pool and level of concurrency so that 77 item pointing to that function and queue that work item on a 86 subsystems and drivers queue work items on and the backend mechanism [all …]
/kernel/linux/linux-5.10/Documentation/networking/
D	af_xdp.rst	13 This document assumes that the reader is familiar with BPF and XDP. If 24 syscall. Associated with each XSK are two rings: the RX ring and the 25 TX ring. A socket can receive packets on the RX ring and it can send 26 packets on the TX ring. These rings are registered and sized with the 27 setsockopts XDP_RX_RING and XDP_TX_RING, respectively. It is mandatory 30 UMEM. RX and TX can share the same UMEM so that a packet does not have 31 to be copied between RX and TX. Moreover, if a packet needs to be kept 33 to that packet can be changed to point to another and reused right 42 UMEM also has two rings: the FILL ring and the COMPLETION ring. The 47 kernel has transmitted completely and can now be used again by user [all …]
/kernel/linux/linux-4.19/Documentation/fb/
D	api.txt	11 with frame buffer devices. In-kernel APIs between device drivers and the frame 15 behaviours differ in subtle (and not so subtle) ways. This document describes 23 Device and driver capabilities are reported in the fixed screen information 33 expect from the device and driver. 42 2. Types and visuals 49 Formats are described by frame buffer types and visuals. Some visuals require 51 bits_per_pixel, grayscale, red, green, blue and transp fields. 53 Visuals describe how color information is encoded and assembled to create 55 types and visuals are supported. 63 Padding at end of lines may be present and is then reported through the fixed [all …]
/kernel/linux/linux-5.10/Documentation/fb/
D	api.rst	12 with frame buffer devices. In-kernel APIs between device drivers and the frame 16 behaviours differ in subtle (and not so subtle) ways. This document describes 24 Device and driver capabilities are reported in the fixed screen information 34 expect from the device and driver. 43 2. Types and visuals 50 Formats are described by frame buffer types and visuals. Some visuals require 52 bits_per_pixel, grayscale, red, green, blue and transp fields. 54 Visuals describe how color information is encoded and assembled to create 56 types and visuals are supported. 64 Padding at end of lines may be present and is then reported through the fixed [all …]

12 3 4 5 6 7 8 9 10 >>...526