| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/bus/ |
| D | renesas,bsc.yaml | 3 $id: http://devicetree.org/schemas/bus/renesas,bsc.yaml#
6 title: Renesas Bus State Controller (BSC)
12 The Renesas Bus State Controller (BSC, sometimes called "LBSC within Bus
18 While the BSC is a fairly simple memory-mapped bus, it may be part of a
20 connected to the BSC can be accessed, the PM domain containing the BSC
21 must be powered on, and the functional clock driving the BSC must be
24 The bindings for the BSC extend the bindings for "simple-pm-bus".
33 - renesas,bsc-r8a73a4 # R-Mobile APE6 (r8a73a4)
34 - renesas,bsc-sh73a0 # SH-Mobile AG5 (sh73a0)
35 - const: renesas,bsc
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/bus/ |
| D | renesas,bsc.txt | 1 Renesas Bus State Controller (BSC)
4 The Renesas Bus State Controller (BSC, sometimes called "LBSC within Bus
9 While the BSC is a fairly simple memory-mapped bus, it may be part of a PM
11 Before a device connected to the BSC can be accessed, the PM domain
12 containing the BSC must be powered on, and the functional clock
13 driving the BSC must be enabled.
15 The bindings for the BSC extend the bindings for "simple-pm-bus".
19 - compatible: Must contain an SoC-specific value, and "renesas,bsc" and
22 "renesas,bsc-r8a73a4" for R-Mobile APE6 (r8a73a4)
23 "renesas,bsc-sh73a0" for SH-Mobile AG5 (sh73a0)
[all …]
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| D | simple-pm-bus.txt | 34 bsc: bus@fec10000 {
35 compatible = "renesas,bsc-sh73a0", "renesas,bsc",
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/memory-controllers/ |
| D | renesas,h8300-bsc.txt | 4 - compatible: Must be "renesas,h8300-bsc".
5 - reg: Base address and length of BSC registers.
8 bsc: memory-controller@fee01e {
9 compatible = "renesas,h8300h-bsc", "renesas,h8300-bsc";
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/ |
| D | renesas,h8300-bsc.txt | 4 - compatible: Must be "renesas,h8300-bsc".
5 - reg: Base address and length of BSC registers.
8 bsc: memory-controller@fee01e {
9 compatible = "renesas,h8300h-bsc", "renesas,h8300-bsc";
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| /kernel/linux/linux-4.19/drivers/staging/board/ |
| D | board.c | 122 int __init board_staging_register_clock(const struct board_staging_clk *bsc) in board_staging_register_clock() argument
126 pr_debug("Aliasing clock %s for con_id %s dev_id %s\n", bsc->clk, in board_staging_register_clock()
127 bsc->con_id, bsc->dev_id); in board_staging_register_clock()
128 error = clk_add_alias(bsc->con_id, bsc->dev_id, bsc->clk, NULL); in board_staging_register_clock()
130 pr_err("Failed to alias clock %s (%d)\n", bsc->clk, error); in board_staging_register_clock()
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| /kernel/linux/linux-5.10/drivers/staging/board/ |
| D | board.c | 122 int __init board_staging_register_clock(const struct board_staging_clk *bsc) in board_staging_register_clock() argument
126 pr_debug("Aliasing clock %s for con_id %s dev_id %s\n", bsc->clk, in board_staging_register_clock()
127 bsc->con_id, bsc->dev_id); in board_staging_register_clock()
128 error = clk_add_alias(bsc->con_id, bsc->dev_id, bsc->clk, NULL); in board_staging_register_clock()
130 pr_err("Failed to alias clock %s (%d)\n", bsc->clk, error); in board_staging_register_clock()
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/i2c/ |
| D | brcm,brcmstb-i2c.yaml | 7 title: Broadcom STB BSC IIC Master Controller
26 - description: BSC register range
31 - const: bsc
93 reg-names = "bsc", "auto-i2c";
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| /kernel/linux/linux-4.19/drivers/gpu/drm/msm/disp/mdp4/ |
| D | mdp4_dtv_encoder.c | 29 uint32_t bsc; member
53 mdp4_dtv_encoder->bsc = msm_bus_scale_register_client( in bs_init()
55 DBG("bus scale client: %08x", mdp4_dtv_encoder->bsc); in bs_init()
64 if (mdp4_dtv_encoder->bsc) { in bs_fini()
65 msm_bus_scale_unregister_client(mdp4_dtv_encoder->bsc); in bs_fini()
66 mdp4_dtv_encoder->bsc = 0; in bs_fini()
72 if (mdp4_dtv_encoder->bsc) { in bs_set()
74 msm_bus_scale_client_update_request(mdp4_dtv_encoder->bsc, idx); in bs_set()
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| D | mdp4_lcdc_encoder.c | 32 uint32_t bsc; member
55 mdp4_lcdc_encoder->bsc = msm_bus_scale_register_client( in bs_init()
57 DBG("lvds : bus scale client: %08x", mdp4_lcdc_encoder->bsc); in bs_init()
63 if (mdp4_lcdc_encoder->bsc) { in bs_fini()
64 msm_bus_scale_unregister_client(mdp4_lcdc_encoder->bsc); in bs_fini()
65 mdp4_lcdc_encoder->bsc = 0; in bs_fini()
71 if (mdp4_lcdc_encoder->bsc) { in bs_set()
73 msm_bus_scale_client_update_request(mdp4_lcdc_encoder->bsc, idx); in bs_set()
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| /kernel/linux/linux-4.19/arch/h8300/boot/dts/ |
| D | h8300h_sim.dts | 60 bsc: memory-controller@fee01e { label
61 compatible = "renesas,h8300h-bsc", "renesas,h8300-bsc";
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| D | h8s_sim.dts | 66 bsc: memory-controller@fffec0 { label
67 compatible = "renesas,h8s-bsc", "renesas,h8300-bsc";
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| D | edosk2674.dts | 67 bsc: memory-controller@fffec0 { label
68 compatible = "renesas,h8s-bsc", "renesas,h8300-bsc";
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| /kernel/linux/linux-5.10/arch/h8300/boot/dts/ |
| D | h8300h_sim.dts | 60 bsc: memory-controller@fee01e { label
61 compatible = "renesas,h8300h-bsc", "renesas,h8300-bsc";
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| D | h8s_sim.dts | 66 bsc: memory-controller@fffec0 { label
67 compatible = "renesas,h8s-bsc", "renesas,h8300-bsc";
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| D | edosk2674.dts | 67 bsc: memory-controller@fffec0 { label
68 compatible = "renesas,h8s-bsc", "renesas,h8300-bsc";
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| /kernel/linux/linux-4.19/drivers/i2c/busses/ |
| D | i2c-brcmstb.c | 30 * PER_I2C/BSC count register mask depends on 1 byte/4 byte data register
39 /* BSC CTL register field definitions */
69 /* BSC data transfer direction */
72 /* BSC data transfer direction combined format */
79 /* BSC block register map structure to cache fields to be written */
208 /* Enable BSC CTL interrupt line */ in brcmstb_i2c_enable_disable_irq()
211 /* Disable BSC CTL interrupt line */ in brcmstb_i2c_enable_disable_irq()
306 /* enable BSC CTL interrupt line */ in brcmstb_send_i2c_cmd()
335 /* Actual data transfer through the BSC master */
625 /* disable the bsc interrupt line */ in brcmstb_i2c_probe()
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| /kernel/linux/linux-5.10/drivers/i2c/busses/ |
| D | i2c-brcmstb.c | 30 * PER_I2C/BSC count register mask depends on 1 byte/4 byte data register
39 /* BSC CTL register field definitions */
69 /* BSC data transfer direction */
72 /* BSC data transfer direction combined format */
79 /* BSC block register map structure to cache fields to be written */
206 /* Enable BSC CTL interrupt line */ in brcmstb_i2c_enable_disable_irq()
209 /* Disable BSC CTL interrupt line */ in brcmstb_i2c_enable_disable_irq()
304 /* enable BSC CTL interrupt line */ in brcmstb_send_i2c_cmd()
333 /* Actual data transfer through the BSC master */
652 /* disable the bsc interrupt line */ in brcmstb_i2c_probe()
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| /kernel/linux/linux-5.10/arch/h8300/kernel/ |
| D | setup.c | 184 struct device_node *bsc; in access_timing() local
190 bsc = of_find_compatible_node(NULL, NULL, "renesas,h8300-bsc"); in access_timing()
191 base = of_iomap(bsc, 0); in access_timing()
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| /kernel/linux/linux-4.19/arch/h8300/kernel/ |
| D | setup.c | 187 struct device_node *bsc; in access_timing() local
193 bsc = of_find_compatible_node(NULL, NULL, "renesas,h8300-bsc"); in access_timing()
194 base = of_iomap(bsc, 0); in access_timing()
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| /kernel/linux/linux-4.19/drivers/gpu/drm/msm/disp/mdp5/ |
| D | mdp5_encoder.c | 61 mdp5_encoder->bsc = msm_bus_scale_register_client( in bs_init()
63 DBG("bus scale client: %08x", mdp5_encoder->bsc); in bs_init()
68 if (mdp5_encoder->bsc) { in bs_fini()
69 msm_bus_scale_unregister_client(mdp5_encoder->bsc); in bs_fini()
70 mdp5_encoder->bsc = 0; in bs_fini()
76 if (mdp5_encoder->bsc) { in bs_set()
83 msm_bus_scale_client_update_request(mdp5_encoder->bsc, idx); in bs_set()
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| /kernel/linux/linux-5.10/arch/sh/include/cpu-sh4/cpu/ |
| D | sh7722.h | 10 * MD3: BSC - Area0 Bus Width (16/32-bit) [CS0BCR.9,10]
11 * MD5: BSC - Endian Mode (L: Big, H: Little) [CMNCR.3]
148 /* BSC */
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| D | sh7723.h | 10 * MD3: BSC - Area0 Bus Width (16/32-bit) [CS0BCR.9,10]
11 * MD5: BSC - Endian Mode (L: Big, H: Little) [CMNCR.3]
247 /* BSC */
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| /kernel/linux/linux-4.19/arch/sh/include/cpu-sh4/cpu/ |
| D | sh7722.h | 10 * MD3: BSC - Area0 Bus Width (16/32-bit) [CS0BCR.9,10]
11 * MD5: BSC - Endian Mode (L: Big, H: Little) [CMNCR.3]
148 /* BSC */
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| D | sh7723.h | 10 * MD3: BSC - Area0 Bus Width (16/32-bit) [CS0BCR.9,10]
11 * MD5: BSC - Endian Mode (L: Big, H: Little) [CMNCR.3]
247 /* BSC */
|