Searched full:beats (Results 1 – 25 of 38) sorted by relevance
12
8 …e data channels between the core and the SCU. If both read and write data beats are transferred on…
48 u32 beats = (qce->burst_size >> 3) - 1; in qce_config_reg() local52 config = (beats << REQ_SIZE_SHIFT) & REQ_SIZE_MASK; in qce_config_reg()
150 u32 beats = (qce->burst_size >> 3) - 1; in qce_config_reg() local154 config = (beats << REQ_SIZE_SHIFT) & REQ_SIZE_MASK; in qce_config_reg()
153 o pbl: the Programmable Burst Length is maximum number of beats to227 o aal: Address-Aligned Beats
96 inactive (high) between data beats of a burst write.
46 - snps,aal Address-Aligned Beats
18 * Port B isn't wired (why - beats me)
19 * Port B isn't wired (why - beats me)
44 * IE Header; beats me.
4 Linux beats them ALL! While all other OS's are TALKING about direct
218 Use Address-Aligned Beats
270 #define SDRAM_BL 8 /* # of beats in a burst */
274 #define SDRAM_BL 8 /* # of beats in a burst */
81 #define COMPASS 100 /* beats per minute */
552 5) Enable Address Aligned Beats::
293 * If number of beats fit in several whole bursts in stm32_dma_fifo_threshold_is_allowed()
559 unit to use? Beats me. My way is to always pick the transfer
985 /* O_PATH beats everything else. */ in build_open_how()
294 * If number of beats fit in several whole bursts in stm32_dma_fifo_threshold_is_allowed()
398 * or a register with the amount of bursts/beats/bytes that have been
897 pr_debug("Missed timer beats: %" PRIu64 "\n", c-1); in perf_kvm__handle_timerfd()
891 pr_debug("Missed timer beats: %" PRIu64 "\n", c-1); in perf_kvm__handle_timerfd()