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/kernel/linux/linux-4.19/drivers/clk/ingenic/
Dcgu.c2 * Ingenic SoC CGU driver
28 #include "cgu.h"
34 * @cgu: reference to the CGU whose registers should be read
38 * caller must hold cgu->lock.
43 ingenic_cgu_gate_get(struct ingenic_cgu *cgu, in ingenic_cgu_gate_get() argument
46 return !!(readl(cgu->base + info->reg) & BIT(info->bit)) in ingenic_cgu_gate_get()
52 * @cgu: reference to the CGU whose registers should be modified
58 * The caller must hold cgu->lock.
61 ingenic_cgu_gate_set(struct ingenic_cgu *cgu, in ingenic_cgu_gate_set() argument
64 u32 clkgr = readl(cgu->base + info->reg); in ingenic_cgu_gate_set()
[all …]
Djz4740-cgu.c2 * Ingenic JZ4740 SoC CGU driver
21 #include <dt-bindings/clock/jz4740-cgu.h>
23 #include "cgu.h"
25 /* CGU register offsets */
54 static struct ingenic_cgu *cgu; variable
220 cgu = ingenic_cgu_new(jz4740_cgu_clocks, in jz4740_cgu_init()
222 if (!cgu) { in jz4740_cgu_init()
223 pr_err("%s: failed to initialise CGU\n", __func__); in jz4740_cgu_init()
227 retval = ingenic_cgu_register_clocks(cgu); in jz4740_cgu_init()
229 pr_err("%s: failed to register CGU Clocks\n", __func__); in jz4740_cgu_init()
[all …]
Dcgu.h2 * Ingenic SoC CGU driver
27 * @reg: the offset of the PLL's control register within the CGU
67 * @reg: offset of the mux control register within the CGU
80 * @reg: offset of the divider control register within the CGU
112 * @reg: offset of the gate control register within the CGU
137 * within the clock_info array of the CGU, or -1 in entries
178 * struct ingenic_cgu - data about the CGU
179 * @np: the device tree node that caused the CGU to be probed
180 * @base: the ioremap'ed base address of the CGU registers
183 * @lock: lock to be held whilst manipulating CGU registers
[all …]
/kernel/linux/linux-5.10/drivers/clk/ingenic/
Dcgu.c3 * Ingenic SoC CGU driver
23 #include "cgu.h"
30 return &clk->cgu->clock_info[clk->idx]; in to_clk_info()
35 * @cgu: reference to the CGU whose registers should be read
39 * caller must hold cgu->lock.
44 ingenic_cgu_gate_get(struct ingenic_cgu *cgu, in ingenic_cgu_gate_get() argument
47 return !!(readl(cgu->base + info->reg) & BIT(info->bit)) in ingenic_cgu_gate_get()
53 * @cgu: reference to the CGU whose registers should be modified
59 * The caller must hold cgu->lock.
62 ingenic_cgu_gate_set(struct ingenic_cgu *cgu, in ingenic_cgu_gate_set() argument
[all …]
DKconfig9 bool "Ingenic JZ4740 CGU driver"
13 Support the clocks provided by the CGU hardware on Ingenic JZ4740
19 bool "Ingenic JZ4725B CGU driver"
23 Support the clocks provided by the CGU hardware on Ingenic JZ4725B
29 bool "Ingenic JZ4770 CGU driver"
33 Support the clocks provided by the CGU hardware on Ingenic JZ4770
39 bool "Ingenic JZ4780 CGU driver"
43 Support the clocks provided by the CGU hardware on Ingenic JZ4780
49 bool "Ingenic X1000 CGU driver"
53 Support the clocks provided by the CGU hardware on Ingenic X1000
[all …]
Dcgu.h3 * Ingenic SoC CGU driver
19 * @reg: the offset of the PLL's control register within the CGU
41 * @bypass_reg: the offset of the bypass control register within the CGU
63 * @reg: offset of the mux control register within the CGU
76 * @reg: offset of the divider control register within the CGU
111 * @reg: offset of the gate control register within the CGU
136 * within the clock_info array of the CGU, or -1 in entries
177 * struct ingenic_cgu - data about the CGU
178 * @np: the device tree node that caused the CGU to be probed
179 * @base: the ioremap'ed base address of the CGU registers
[all …]
DMakefile2 obj-$(CONFIG_INGENIC_CGU_COMMON) += cgu.o pm.o
3 obj-$(CONFIG_INGENIC_CGU_JZ4740) += jz4740-cgu.o
4 obj-$(CONFIG_INGENIC_CGU_JZ4725B) += jz4725b-cgu.o
5 obj-$(CONFIG_INGENIC_CGU_JZ4770) += jz4770-cgu.o
6 obj-$(CONFIG_INGENIC_CGU_JZ4780) += jz4780-cgu.o
7 obj-$(CONFIG_INGENIC_CGU_X1000) += x1000-cgu.o
8 obj-$(CONFIG_INGENIC_CGU_X1830) += x1830-cgu.o
Dx1000-cgu.c3 * X1000 SoC CGU driver
12 #include <dt-bindings/clock/x1000-cgu.h>
14 #include "cgu.h"
17 /* CGU register offsets */
61 static struct ingenic_cgu *cgu; variable
69 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in x1000_otg_phy_recalc_rate()
121 spin_lock_irqsave(&cgu->lock, flags); in x1000_otg_phy_set_rate()
123 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in x1000_otg_phy_set_rate()
126 writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); in x1000_otg_phy_set_rate()
128 spin_unlock_irqrestore(&cgu->lock, flags); in x1000_otg_phy_set_rate()
[all …]
Djz4780-cgu.c3 * Ingenic JZ4780 SoC CGU driver
16 #include <dt-bindings/clock/jz4780-cgu.h>
18 #include "cgu.h"
21 /* CGU register offsets */
103 static struct ingenic_cgu *cgu; variable
111 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in jz4780_otg_phy_recalc_rate()
173 spin_lock_irqsave(&cgu->lock, flags); in jz4780_otg_phy_set_rate()
175 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in jz4780_otg_phy_set_rate()
178 writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); in jz4780_otg_phy_set_rate()
180 spin_unlock_irqrestore(&cgu->lock, flags); in jz4780_otg_phy_set_rate()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dlpc1850-ccu.txt3 Each CGU base clock has several clock branches which can be turned on
23 from the CGU to the specific CCU. See mapping of base clocks
27 from the CGU to the specific CCU. Valid CCU clock names:
47 clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>,
48 <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>,
49 <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
50 <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>;
61 clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
62 <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
63 <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
[all …]
Dingenic,cgu.yaml4 $id: http://devicetree.org/schemas/clock/ingenic,cgu.yaml#
7 title: Ingenic SoCs CGU devicetree bindings
10 The CGU in an Ingenic SoC provides all the clocks generated on-chip. It
23 - ingenic,jz4740-cgu
24 - ingenic,jz4725b-cgu
25 - ingenic,jz4770-cgu
26 - ingenic,jz4780-cgu
27 - ingenic,x1000-cgu
28 - ingenic,x1830-cgu
50 - ingenic,jz4740-cgu
[all …]
Dlpc1850-cgu.txt1 * NXP LPC1850 Clock Generation Unit (CGU)
3 The CGU generates multiple independent clocks for the core and the
9 The CGU selects the inputs to the clock generators from multiple
23 Should be "nxp,lpc1850-cgu"
32 sources to the CGU. The list shall be in the following
36 number provided by the CGU.
39 the clocks provided by the CGU.
41 Which base clocks that are available on the CGU depends on the
116 cgu: clock-controller@40050000 {
117 compatible = "nxp,lpc1850-cgu";
[all …]
Dintel,cgu-lgm.yaml4 $id: http://devicetree.org/schemas/clock/intel,cgu-lgm.yaml#
7 title: Intel Lightning Mountain SoC's Clock Controller(CGU) Binding
13 Lightning Mountain(LGM) SoC's Clock Generation Unit(CGU) driver provides
14 all means to access the CGU hardware module in order to generate a series
23 const: intel,cgu-lgm
40 cgu: clock-controller@e0200000 {
41 compatible = "intel,cgu-lgm";
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/clock/
Dlpc1850-ccu.txt3 Each CGU base clock has several clock branches which can be turned on
23 from the CGU to the specific CCU. See mapping of base clocks
27 from the CGU to the specific CCU. Valid CCU clock names:
47 clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>,
48 <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>,
49 <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
50 <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>;
61 clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
62 <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
63 <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
[all …]
Dingenic,cgu.txt1 Ingenic SoC CGU binding
3 The CGU in an Ingenic SoC provides all the clocks generated on-chip. It
9 - compatible : Should be "ingenic,<soctype>-cgu".
10 For example "ingenic,jz4740-cgu" or "ingenic,jz4780-cgu".
11 - reg : The address & length of the CGU registers.
12 - clocks : List of phandle & clock specifiers for clocks external to the CGU.
18 may be found in <dt-bindings/clock/<soctype>-cgu.h>.
23 cgu: jz4740-cgu {
24 compatible = "ingenic,jz4740-cgu";
30 clocks = <&cgu JZ4740_CLK_UART0>;
[all …]
Dlpc1850-cgu.txt1 * NXP LPC1850 Clock Generation Unit (CGU)
3 The CGU generates multiple independent clocks for the core and the
9 The CGU selects the inputs to the clock generators from multiple
23 Should be "nxp,lpc1850-cgu"
32 sources to the CGU. The list shall be in the following
36 number provided by the CGU.
39 the clocks provided by the CGU.
41 Which base clocks that are available on the CGU depends on the
116 cgu: clock-controller@40050000 {
117 compatible = "nxp,lpc1850-cgu";
[all …]
/kernel/linux/linux-5.10/arch/mips/boot/dts/ingenic/
Djz4740.dtsi2 #include <dt-bindings/clock/jz4740-cgu.h>
19 clocks = <&cgu JZ4740_CLK_CCLK>;
53 cgu: jz4740-cgu@10000000 { label
54 compatible = "ingenic,jz4740-cgu";
72 clocks = <&cgu JZ4740_CLK_RTC>,
73 <&cgu JZ4740_CLK_EXT>,
74 <&cgu JZ4740_CLK_PCLK>,
75 <&cgu JZ4740_CLK_TCU>;
114 clocks = <&cgu JZ4740_CLK_RTC>;
195 clocks = <&cgu JZ4740_CLK_AIC>,
[all …]
Djz4770.dtsi2 #include <dt-bindings/clock/jz4770-cgu.h>
19 clocks = <&cgu JZ4770_CLK_CCLK>;
53 cgu: jz4770-cgu@10000000 { label
54 compatible = "ingenic,jz4770-cgu", "simple-mfd";
69 clocks = <&cgu JZ4770_CLK_OTG_PHY>;
84 clocks = <&cgu JZ4770_CLK_RTC>,
85 <&cgu JZ4770_CLK_EXT>,
86 <&cgu JZ4770_CLK_PCLK>;
241 clocks = <&cgu JZ4770_CLK_AIC>, <&cgu JZ4770_CLK_I2S>,
242 <&cgu JZ4770_CLK_EXT>, <&cgu JZ4770_CLK_PLL0>;
[all …]
Djz4725b.dtsi2 #include <dt-bindings/clock/jz4725b-cgu.h>
19 clocks = <&cgu JZ4725B_CLK_CCLK>;
53 cgu: clock-controller@10000000 { label
54 compatible = "ingenic,jz4725b-cgu";
72 clocks = <&cgu JZ4725B_CLK_RTC>,
73 <&cgu JZ4725B_CLK_EXT>,
74 <&cgu JZ4725B_CLK_PCLK>,
75 <&cgu JZ4725B_CLK_TCU>;
123 clocks = <&cgu JZ4725B_CLK_RTC>;
201 clocks = <&cgu JZ4725B_CLK_AIC>,
[all …]
Djz4780.dtsi2 #include <dt-bindings/clock/jz4780-cgu.h>
20 clocks = <&cgu JZ4780_CLK_CPU>;
29 clocks = <&cgu JZ4780_CLK_CORE1>;
63 cgu: jz4780-cgu@10000000 { label
64 compatible = "ingenic,jz4780-cgu";
84 clocks = <&cgu JZ4780_CLK_RTCLK>,
85 <&cgu JZ4780_CLK_EXCLK>,
86 <&cgu JZ4780_CLK_PCLK>;
135 clocks = <&cgu JZ4780_CLK_RTCLK>;
262 clocks = <&ext>, <&cgu JZ4780_CLK_UART0>;
[all …]
Dx1000.dtsi3 #include <dt-bindings/clock/x1000-cgu.h>
20 clocks = <&cgu X1000_CLK_CPU>;
54 cgu: x1000-cgu@10000000 { label
55 compatible = "ingenic,x1000-cgu";
73 clocks = <&cgu X1000_CLK_RTCLK>,
74 <&cgu X1000_CLK_EXCLK>,
75 <&cgu X1000_CLK_PCLK>;
100 clocks = <&cgu X1000_CLK_RTCLK>;
178 clocks = <&exclk>, <&cgu X1000_CLK_UART0>;
191 clocks = <&exclk>, <&cgu X1000_CLK_UART1>;
[all …]
Dx1830.dtsi3 #include <dt-bindings/clock/x1830-cgu.h>
20 clocks = <&cgu X1830_CLK_CPU>;
54 cgu: x1830-cgu@10000000 { label
55 compatible = "ingenic,x1830-cgu";
73 clocks = <&cgu X1830_CLK_RTCLK
74 &cgu X1830_CLK_EXCLK
75 &cgu X1830_CLK_PCLK>;
100 clocks = <&cgu X1830_CLK_RTCLK>;
178 clocks = <&exclk>, <&cgu X1830_CLK_UART0>;
191 clocks = <&exclk>, <&cgu X1830_CLK_UART1>;
[all …]
/kernel/linux/linux-4.19/arch/mips/boot/dts/ingenic/
Djz4780.dtsi2 #include <dt-bindings/clock/jz4780-cgu.h>
39 cgu: jz4780-cgu@10000000 { label
40 compatible = "ingenic,jz4780-cgu";
56 clocks = <&cgu JZ4780_CLK_RTCLK>;
184 clocks = <&ext>, <&cgu JZ4780_CLK_UART0>;
197 clocks = <&ext>, <&cgu JZ4780_CLK_UART1>;
210 clocks = <&ext>, <&cgu JZ4780_CLK_UART2>;
223 clocks = <&ext>, <&cgu JZ4780_CLK_UART3>;
236 clocks = <&ext>, <&cgu JZ4780_CLK_UART4>;
246 clocks = <&cgu JZ4780_CLK_RTCLK>;
[all …]
Djz4740.dtsi2 #include <dt-bindings/clock/jz4740-cgu.h>
38 cgu: jz4740-cgu@10000000 { label
39 compatible = "ingenic,jz4740-cgu";
52 clocks = <&cgu JZ4740_CLK_RTC>;
63 clocks = <&cgu JZ4740_CLK_RTC>;
142 clocks = <&ext>, <&cgu JZ4740_CLK_UART0>;
153 clocks = <&ext>, <&cgu JZ4740_CLK_UART1>;
161 clocks = <&cgu JZ4740_CLK_UHC>;
162 assigned-clocks = <&cgu JZ4740_CLK_UHC>;
Djz4770.dtsi3 #include <dt-bindings/clock/jz4770-cgu.h>
39 cgu: jz4770-cgu@10000000 { label
40 compatible = "ingenic,jz4770-cgu";
151 clocks = <&ext>, <&cgu JZ4770_CLK_UART0>;
164 clocks = <&ext>, <&cgu JZ4770_CLK_UART1>;
177 clocks = <&ext>, <&cgu JZ4770_CLK_UART2>;
190 clocks = <&ext>, <&cgu JZ4770_CLK_UART3>;
203 clocks = <&cgu JZ4770_CLK_UHC>, <&cgu JZ4770_CLK_UHC_PHY>;
204 assigned-clocks = <&cgu JZ4770_CLK_UHC>;

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