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/kernel/linux/linux-5.10/arch/arm/mach-omap2/
Dcm2_44xx.h3 * OMAP44xx CM2 instance offset macros
25 /* CM2 base address */
31 /* CM2 instances */
46 /* CM2 clockdomain register offsets (from instance start) */
65 /* CM2 */
67 /* CM2.OCP_SOCKET_CM2 register offsets */
73 /* CM2.CKGEN_CM2 register offsets */
153 /* CM2.ALWAYS_ON_CM2 register offsets */
167 /* CM2.CORE_CM2 register offsets */
251 /* CM2.IVAHD_CM2 register offsets */
[all …]
Dcm_common.c34 /* cm2_base: base virtual address of the CM2 IP block (OMAP44xx only) */
41 * omap2_set_globals_cm - set the CM/CM2 base addresses (for early use)
43 * @cm2: CM2 base virtual address (if present on the booted SoC)
47 void __init omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2) in omap2_set_globals_cm() argument
50 cm2_base.va = cm2; in omap2_set_globals_cm()
293 { .compatible = "ti,omap4-cm2", .data = &cm2_data },
Dcm44xx.h10 * OMAP4 has two separate CM blocks, CM1 and CM2. This file contains
Dprcm44xx.h11 * the PRM/CM/PRCM blocks on the OMAP4 devices: PRM, CM1, CM2,
Dcm.h29 extern void omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2);
Dcm2_54xx.h3 * OMAP54xx CM2 instance offset macros
21 /* CM2 base address */
Dcm2_7xx.h3 * DRA7xx CM2 instance offset macros
22 /* CM2 base address */
Dcminst44xx.c11 * or CM2 hardware modules. For example, the EMU_CM CM instance is in
/kernel/linux/linux-4.19/arch/arm/mach-omap2/
Dcm2_44xx.h2 * OMAP44xx CM2 instance offset macros
28 /* CM2 base address */
34 /* CM2 instances */
49 /* CM2 clockdomain register offsets (from instance start) */
68 /* CM2 */
70 /* CM2.OCP_SOCKET_CM2 register offsets */
76 /* CM2.CKGEN_CM2 register offsets */
156 /* CM2.ALWAYS_ON_CM2 register offsets */
170 /* CM2.CORE_CM2 register offsets */
254 /* CM2.IVAHD_CM2 register offsets */
[all …]
Dcm_common.c37 /* cm2_base: base virtual address of the CM2 IP block (OMAP44xx only) */
44 * omap2_set_globals_cm - set the CM/CM2 base addresses (for early use)
46 * @cm2: CM2 base virtual address (if present on the booted SoC)
50 void __init omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2) in omap2_set_globals_cm() argument
53 cm2_base.va = cm2; in omap2_set_globals_cm()
296 { .compatible = "ti,omap4-cm2", .data = &cm2_data },
Dcm44xx.h13 * OMAP4 has two separate CM blocks, CM1 and CM2. This file contains
Dprcm44xx.h14 * the PRM/CM/PRCM blocks on the OMAP4 devices: PRM, CM1, CM2,
Dcm.h32 extern void omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2);
Dcm2_54xx.h2 * OMAP54xx CM2 instance offset macros
24 /* CM2 base address */
Dcm2_7xx.h2 * DRA7xx CM2 instance offset macros
25 /* CM2 base address */
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/omap/
Dprcm.txt19 "ti,omap4-cm2"
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/omap/
Dprcm.txt19 "ti,omap4-cm2"
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/clock/
Dti-clkctrl.txt26 &cm2 {
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dti-clkctrl.txt31 &cm2 {
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/
Dbaikal,bt1-l2-ctl.yaml15 tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible
/kernel/linux/linux-5.10/drivers/memory/
DKconfig70 bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
Dbt1-l2-ctl.c8 * Baikal-T1 CM2 L2-cache Control Block driver.
/kernel/linux/linux-5.10/drivers/bus/
Dbt1-axi.c219 * Performing unaligned read from the memory will cause the CM2 bus in inject_error_store()
/kernel/linux/linux-4.19/arch/mips/kernel/
Dmips-cm.c349 if (revision < CM_REV_CM3) { /* CM2 */ in mips_cm_error_report()
/kernel/linux/linux-5.10/arch/mips/kernel/
Dmips-cm.c387 if (revision < CM_REV_CM3) { /* CM2 */ in mips_cm_error_report()

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