| /kernel/linux/linux-4.19/drivers/isdn/hisax/ |
| D | s0box.c | 23 outb_p(0x1c, padr + 2); in writereg()
24 outb_p(0x14, padr + 2); in writereg()
26 outb_p(0x16, padr + 2); in writereg()
28 outb_p(0x17, padr + 2); in writereg()
29 outb_p(0x14, padr + 2); in writereg()
30 outb_p(0x1c, padr + 2); in writereg()
35 0, 8, 4, 0xc, 2, 0xa, 6, 0xe };
41 outb_p(0x1c, padr + 2); in readreg()
42 outb_p(0x14, padr + 2); in readreg()
44 outb_p(0x16, padr + 2); in readreg()
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| D | amd7930_fn.c | 6 * Author Christoph Ersfeld <info@formula-n.de>
7 * Formula-n Europe AG (www.formula-n.com)
19 * (compressed) debug-logs.
22 * Log D-channel-processing as follows:
24 * 1. Load hisax with card-specific parameters, this example ist for
25 * Formula-n enter:now ISDN PCI and compatible
28 * modprobe hisax type=41 protocol=2 id=gerdes
33 * 2. set debug-level
44 * Programming the driver for Formula-n enter:now ISDN PCI and
45 * necessary this driver for the used Amd 7930 D-channel-controller
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| D | teles3.c | 56 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
58 return (readreg(cs->hw.teles3.isac, offset)); in ReadISAC()
62 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
64 writereg(cs->hw.teles3.isac, offset, value); in WriteISAC()
68 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) in ReadISACfifo() argument
70 read_fifo(cs->hw.teles3.isacfifo, data, size); in ReadISACfifo()
74 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) in WriteISACfifo() argument
76 write_fifo(cs->hw.teles3.isacfifo, data, size); in WriteISACfifo()
80 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) in ReadHSCX() argument
82 return (readreg(cs->hw.teles3.hscx[hscx], offset)); in ReadHSCX()
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| D | niccy.c | 31 #define ISAC_PCI_ADDR 2
38 #define NICCY_PCI 2
78 static u_char ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
80 return readreg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, offset); in ReadISAC()
83 static void WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
85 writereg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, offset, value); in WriteISAC()
88 static void ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) in ReadISACfifo() argument
90 readfifo(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, 0, data, size); in ReadISACfifo()
93 static void WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) in WriteISACfifo() argument
95 writefifo(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, 0, data, size); in WriteISACfifo()
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| D | hfcscard.c | 24 struct IsdnCardState *cs = dev_id; in hfcs_interrupt() local
28 spin_lock_irqsave(&cs->lock, flags); in hfcs_interrupt()
30 (stat = cs->BC_Read_Reg(cs, HFCD_DATA, HFCD_STAT))) { in hfcs_interrupt()
31 val = cs->BC_Read_Reg(cs, HFCD_DATA, HFCD_INT_S1); in hfcs_interrupt()
32 if (cs->debug & L1_DEB_ISAC) in hfcs_interrupt()
33 debugl1(cs, "HFCS: stat(%02x) s1(%02x)", stat, val); in hfcs_interrupt()
34 hfc2bds0_interrupt(cs, val); in hfcs_interrupt()
36 if (cs->debug & L1_DEB_ISAC) in hfcs_interrupt()
37 debugl1(cs, "HFCS: irq_no_irq stat(%02x)", stat); in hfcs_interrupt()
39 spin_unlock_irqrestore(&cs->lock, flags); in hfcs_interrupt()
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| D | avm_pci.c | 27 #define AVM_FRITZ_PNP 2
78 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
83 outb(idx, cs->hw.avm.cfg_reg + 4); in ReadISAC()
84 val = inb(cs->hw.avm.isac + (offset & 0xf)); in ReadISAC()
89 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
93 outb(idx, cs->hw.avm.cfg_reg + 4); in WriteISAC()
94 outb(value, cs->hw.avm.isac + (offset & 0xf)); in WriteISAC()
98 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) in ReadISACfifo() argument
100 outb(AVM_ISAC_FIFO, cs->hw.avm.cfg_reg + 4); in ReadISACfifo()
101 insb(cs->hw.avm.isac, data, size); in ReadISACfifo()
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| D | elsa.c | 36 {"None", "PC", "PCC-8", "PCC-16", "PCF", "PCF-Pro",
38 "PCMCIA-IPAC" };
41 {"?0?", "?1?", "?2?", "?3?", "?4?", "V2.2",
50 #define ELSA_HSCX 2
59 #define ELSA_PCC8 2
83 *** (mehrere Befehle werden durch Bit-Oderung kombiniert) ***
86 /* Config-Register (Read) */
87 #define ELIRQF_TIMER_RUN 0x02 /* Bit 1 des Config-Reg */
88 #define ELIRQF_TIMER_RUN_PCC8 0x01 /* Bit 0 des Config-Reg bei PCC */
89 #define ELSA_IRQ_IDX 0x38 /* Bit 3,4,5 des Config-Reg */
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| D | ix1_micro.c | 3 * low level stuff for ITK ix1-micro Rev.2 isdn cards
6 * Author Klaus-Peter Nischke
7 * Copyright by Klaus-Peter Nischke, ITK AG
14 * Klaus-Peter Nischke
34 #define ISAC_COMMAND_OFFSET 2
36 #define HSCX_COMMAND_OFFSET 2
76 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
78 return (readreg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, offset)); in ReadISAC()
82 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
84 writereg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, offset, value); in WriteISAC()
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| D | sedlbauer.c | 6 * support for the Sedlbauer ISDN-Controller PC/104 and
11 * Copyright by Marcus Niemann <niemann@www-bib.fh-bielefeld.de>
24 * ---------------------------------------------------------------------
25 * Speed Card ISAC_HSCX DIP-SWITCH
30 * ISDN PC/104 IPAC DIP-SWITCH
65 #define SEDL_SPEED_STAR 2
76 #define SEDL_CHIP_ISAC_ISAR 2
80 #define SEDL_BUS_PCI 2
88 #define SEDL_HSCX_ISA_ISAC 2
94 #define SEDL_HSCX_PCMCIA_HSCX 2
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| D | teleint.c | 32 while (ret && --max_delay) in readreg()
52 while (ret && --max_delay) in readfifo()
71 while (ret && --max_delay) in writereg()
90 while (ret && --max_delay) in writefifo()
103 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
105 cs->hw.hfc.cip = offset; in ReadISAC()
106 return (readreg(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, offset)); in ReadISAC()
110 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
112 cs->hw.hfc.cip = offset; in WriteISAC()
113 writereg(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, offset, value); in WriteISAC()
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| D | enternow_pci.c | 3 * enternow_pci.c Card-specific routines for
4 * Formula-n enter:now ISDN PCI ab
9 * Author Christoph Ersfeld <info@formula-n.de>
10 * Formula-n Europe AG (www.formula-n.com)
17 * This driver interfaces to netjet.c which performs B-channel
26 * (compressed) debug-logs.
29 * Log D-channel-processing as follows:
31 * 1. Load hisax with card-specific parameters, this example ist for
32 * Formula-n enter:now ISDN PCI and compatible
35 * modprobe hisax type=41 protocol=2 id=gerdes
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| D | hfc_sx.c | 3 * level driver for Cologne Chip Designs hfc-s+/sp based cards
25 /* IRQ-table for CCDs demo board */
33 * ISA-SLOT Signal PIN
46 0, 0, 0, 0, 0, 2, 1, 0, 0, 0, 3, 4, 5, 0, 0, 6
50 0, 0, 0, 7, 0, 1, 0, 0, 0, 2, 3, 4, 5, 0, 0, 6
62 Write_hfc(struct IsdnCardState *cs, u_char regnum, u_char val) in Write_hfc() argument
64 byteout(cs->hw.hfcsx.base + 1, regnum); in Write_hfc()
65 byteout(cs->hw.hfcsx.base, val); in Write_hfc()
69 Read_hfc(struct IsdnCardState *cs, u_char regnum) in Read_hfc() argument
73 byteout(cs->hw.hfcsx.base + 1, regnum); in Read_hfc()
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| D | isar.c | 19 #define DUMP_MBOXFRAME 2
27 static int frm_extra_delay = 2;
31 static void isar_setup(struct IsdnCardState *cs);
36 waitforHIA(struct IsdnCardState *cs, int timeout) in waitforHIA() argument
39 while ((cs->BC_Read_Reg(cs, 0, ISAR_HIA) & 1) && timeout) { in waitforHIA()
41 timeout--; in waitforHIA()
50 sendmsg(struct IsdnCardState *cs, u_char his, u_char creg, u_char len, in sendmsg() argument
55 if (!waitforHIA(cs, 4000)) in sendmsg()
58 if (cs->debug & L1_DEB_HSCX) in sendmsg()
59 debugl1(cs, "sendmsg(%02x,%02x,%d)", his, creg, len); in sendmsg()
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| D | isac.c | 31 void ISACVersion(struct IsdnCardState *cs, char *s) in ISACVersion() argument
35 val = cs->readisac(cs, ISAC_RBCH); in ISACVersion()
40 ph_command(struct IsdnCardState *cs, unsigned int command) in ph_command() argument
42 if (cs->debug & L1_DEB_ISAC) in ph_command()
43 debugl1(cs, "ph_command %x", command); in ph_command()
44 cs->writeisac(cs, ISAC_CIX0, (command << 2) | 3); in ph_command()
49 isac_new_ph(struct IsdnCardState *cs) in isac_new_ph() argument
51 switch (cs->dc.isac.ph_state) { in isac_new_ph()
54 ph_command(cs, ISAC_CMD_DUI); in isac_new_ph()
55 l1_msg(cs, HW_RESET | INDICATION, NULL); in isac_new_ph()
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| D | icc.c | 32 ICCVersion(struct IsdnCardState *cs, char *s) in ICCVersion() argument
36 val = cs->readisac(cs, ICC_RBCH); in ICCVersion()
41 ph_command(struct IsdnCardState *cs, unsigned int command) in ph_command() argument
43 if (cs->debug & L1_DEB_ISAC) in ph_command()
44 debugl1(cs, "ph_command %x", command); in ph_command()
45 cs->writeisac(cs, ICC_CIX0, (command << 2) | 3); in ph_command()
50 icc_new_ph(struct IsdnCardState *cs) in icc_new_ph() argument
52 switch (cs->dc.icc.ph_state) { in icc_new_ph()
54 ph_command(cs, ICC_CMD_DI); in icc_new_ph()
55 l1_msg(cs, HW_RESET | INDICATION, NULL); in icc_new_ph()
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| D | avm_a1.c | 56 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
58 return (readreg(cs->hw.avm.isac, offset)); in ReadISAC()
62 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
64 writereg(cs->hw.avm.isac, offset, value); in WriteISAC()
68 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) in ReadISACfifo() argument
70 read_fifo(cs->hw.avm.isacfifo, data, size); in ReadISACfifo()
74 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) in WriteISACfifo() argument
76 write_fifo(cs->hw.avm.isacfifo, data, size); in WriteISACfifo()
80 ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset) in ReadHSCX() argument
82 return (readreg(cs->hw.avm.hscx[hscx], offset)); in ReadHSCX()
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| D | isurf.c | 3 * low level stuff for Siemens I-Surf/I-Talk cards
26 #define ISURF_ISAC_RESET 2
37 ReadISAC(struct IsdnCardState *cs, u_char offset) in ReadISAC() argument
39 return (readb(cs->hw.isurf.isac + offset)); in ReadISAC()
43 WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value) in WriteISAC() argument
45 writeb(value, cs->hw.isurf.isac + offset); mb(); in WriteISAC()
49 ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size) in ReadISACfifo() argument
53 data[i] = readb(cs->hw.isurf.isac); in ReadISACfifo()
57 WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size) in WriteISACfifo() argument
61 writeb(data[i], cs->hw.isurf.isac); mb(); in WriteISACfifo()
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| D | config.c | 37 * 2 Teles 8.0 p0=irq p1=membase
44 * 9 ITK ix1-micro p0=irq p1=iobase
57 * 20 Travers Technologies NETjet-S PCI card
66 * 29 Siemens I-Surf p0=irq p1=iobase p2=memory (from isapnp setup)
72 * 35 HFC 2BDS0 PCI none
74 * 37 HFC 2BDS0 S+/SP p0=irq p1=iobase
75 * 38 Travers Technologies NETspider-U PCI card
76 * 39 HFC 2BDS0-SP PCMCIA p0=irq p1=iobase
78 * 41 Formula-n enter:now ISDN PCI a/b none
88 "Teles PCMCIA", "ITK ix1-micro Rev.2", "Elsa PCMCIA",
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/ |
| D | gen2_engine_cs.c | 1 // SPDX-License-Identifier: MIT
17 u32 cmd, *cs; in gen2_emit_flush() local
23 cs = intel_ring_begin(rq, 2 + 4 * num_store_dw); in gen2_emit_flush()
24 if (IS_ERR(cs)) in gen2_emit_flush()
25 return PTR_ERR(cs); in gen2_emit_flush()
27 *cs++ = cmd; in gen2_emit_flush()
28 while (num_store_dw--) { in gen2_emit_flush()
29 *cs++ = MI_STORE_DWORD_INDEX; in gen2_emit_flush()
30 *cs++ = I915_GEM_HWS_SCRATCH * sizeof(u32); in gen2_emit_flush()
31 *cs++ = 0; in gen2_emit_flush()
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| D | gen7_renderclear.c | 1 // SPDX-License-Identifier: MIT
11 #define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS)) argument
47 * a shader on every HW thread, and clear the thread-local registers. in num_primitives()
51 return bv->max_threads; in num_primitives()
58 switch (INTEL_INFO(i915)->gt) { in batch_get_defaults()
61 bv->max_threads = 70; in batch_get_defaults()
63 case 2: in batch_get_defaults()
64 bv->max_threads = 140; in batch_get_defaults()
67 bv->max_threads = 280; in batch_get_defaults()
70 bv->surface_height = 16 * 16; in batch_get_defaults()
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| /kernel/linux/linux-4.19/drivers/isdn/divert/ |
| D | isdn_divert.c | 61 struct call_struc *cs = from_timer(cs, t, timer); in deflect_timer_expire() local
64 del_timer(&cs->timer); /* delete active timer */ in deflect_timer_expire()
67 switch (cs->akt_state) { in deflect_timer_expire()
69 cs->ics.command = ISDN_CMD_HANGUP; /* cancel action */ in deflect_timer_expire()
70 divert_if.ll_cmd(&cs->ics); in deflect_timer_expire()
72 cs->akt_state = DEFLECT_AUTODEL; /* delete after timeout */ in deflect_timer_expire()
73 cs->timer.expires = jiffies + (HZ * AUTODEL_TIME); in deflect_timer_expire()
74 add_timer(&cs->timer); in deflect_timer_expire()
79 cs->ics.command = ISDN_CMD_REDIR; /* protocol */ in deflect_timer_expire()
80 strlcpy(cs->ics.parm.setup.phone, cs->deflect_dest, sizeof(cs->ics.parm.setup.phone)); in deflect_timer_expire()
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| /kernel/linux/linux-4.19/drivers/gpu/drm/i915/ |
| D | intel_ringbuffer.c | 2 * Copyright © 2008-2010 Intel Corporation
42 * set-context and then emitting the batch.
56 return (head - tail - CACHELINE_BYTES) & (size - 1); in __intel_ring_space()
63 space = __intel_ring_space(ring->head, ring->emit, ring->size); in intel_ring_update_space()
65 ring->space = space; in intel_ring_update_space()
72 u32 cmd, *cs; in gen2_render_ring_flush() local
79 cs = intel_ring_begin(rq, 2); in gen2_render_ring_flush()
80 if (IS_ERR(cs)) in gen2_render_ring_flush()
81 return PTR_ERR(cs); in gen2_render_ring_flush()
83 *cs++ = cmd; in gen2_render_ring_flush()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/ |
| D | ti-aemif.txt | 4 provide a glue-less interface to a variety of asynchronous memory devices like
11 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
12 OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
13 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
17 - compatible: "ti,davinci-aemif"
18 "ti,keystone-aemif"
19 "ti,da850-aemif"
21 - reg: contains offset/length value for AEMIF control registers
24 - #address-cells: Must be 2. The partition number has to be encoded in the
25 first address cell and it may accept values 0..N-1
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/memory-controllers/ |
| D | ti-aemif.txt | 4 provide a glue-less interface to a variety of asynchronous memory devices like
11 Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
12 OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
13 Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
17 - compatible: "ti,davinci-aemif"
18 "ti,keystone-aemif"
19 "ti,da850-aemif"
21 - reg: contains offset/length value for AEMIF control registers
24 - #address-cells: Must be 2. The partition number has to be encoded in the
25 first address cell and it may accept values 0..N-1
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| /kernel/linux/linux-5.10/arch/m68k/include/asm/ |
| D | m5307sim.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5307sim.h -- ColdFire 5307 System Integration Module support.
20 #define MCF_BUSCLK (MCF_CLK / 2)
40 #define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
51 #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
52 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
53 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
54 #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
55 #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
56 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
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