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/kernel/liteos_m/
Darch_spec.md3 ├── arch --- Code of the kernel instruction …
4 │   ├── arm --- ARM32 architecture
5 │   │   ├── arm9 --- ARM9 architecture
6 │   │   │ └── gcc --- Implementation of the GCC toolc…
7 │   │   ├── cortex-m3 --- Cortex-m3 architecture
8 │   │   │ └── keil --- Implementation of the keil tool…
9 │   │   ├── cortex-m33 --- Cortex-m33 architecture
10 │   │   │ │── gcc --- Implementation of the GCC toolc…
11 │   │   │ │ │── NTZ --- Cortex-m33 Non-TrustZone archit…
12 │   │   │ │ └── TZ --- Cortex-m33 TrustZone architectu…
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DREADME.md1 # LiteOS-M Kernel<a name="EN-US_TOPIC_0000001096757661"></a>
3 - [Introduction](#section11660541593)
4 - [Directory Structure](#section161941989596)
5 - [Constraints](#section119744591305)
6 - [Usage](#section3732185231214)
7 - [Contribution](#section1371123476307)
8 - [Repositories Involved](#section1371113476307)
12 …-M is a lightweight operating system kernel designed for the Internet of Things (IoT) field. It fe…
13 **Figure1** shows the architecture of the LiteOS-M kernel.
15 **Figure 1** Architecture of the OpenHarmony LiteOS-M kernel<a name="fig0865152210223"></a>
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DREADME_zh.md1 # LiteOS-M内核<a name="ZH-CN_TOPIC_0000001096757661"></a>
3 - [简介](#section11660541593)
4 - [目录](#section161941989596)
5 - [约束](#section119744591305)
6 - [使用说明](#section3732185231214)
7 - [贡献](#section1371123476307)
8 - [相关仓](#section1371113476307)
12 OpenHarmony LiteOS-M内核是面向IoT领域构建的轻量级物联网操作系统内核，具有小体积、低功耗、高性能的特点，其代码结构简单，主要包括内核最小功能集、内核抽象层、可选组件以及工程目录…
14 **图 1** OpenHarmony LiteOS-M核内核架构图<a name="fig0865152210223"></a>
15 ![](figures/OpenHarmony-LiteOS-M核内核架构图.png "OpenHarmony-LiteOS-M核内核架构图")
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Darch_spec_zh.md3 ├── arch --- 内核指令架构层代码
4 │   ├── arm --- ARM32架构
5 │   │   ├── arm9 --- arm9架构
6 │   │   │ └── gcc --- gcc 编译工具链实现
7 │   │   ├── cortex-m3 --- Cortex-m3架构
8 │   │   │ └── keil --- Keil编译工具链实现
9 │   │   ├── cortex-m33 --- Cortex-m33架构
10 │   │   │ │── gcc --- GCC编译工具链实现
11 │   │   │ │ │── NTZ --- Cortex-m33非TrustZone架构实现
12 │   │   │ │ └── TZ --- Cortex-m33 TrustZone架构实现
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/kernel/linux/linux-4.19/Documentation/arm/stm32/
Dstm32f429-overview.rst5 ------------
7 The STM32F429 is a Cortex-M4 MCU aimed at various applications.
10 - ARM Cortex-M4 up to 180MHz with FPU
11 - 2MB internal Flash Memory
12 - External memory support through FMC controller (PSRAM, SDRAM, NOR, NAND)
13 - I2C, SPI, SAI, CAN, USB OTG, Ethernet controllers
14 - LCD controller & Camera interface
15 - Cryptographic processor
18 ---------
22 …www.st.com/web/en/catalog/mmc/FM141/SC1169/SS1577/LN1806?ecmp=stm32f429-439_pron_pr-ces2014_nov2013
/kernel/linux/linux-5.10/Documentation/arm/stm32/
Dstm32f429-overview.rst6 ------------
8 The STM32F429 is a Cortex-M4 MCU aimed at various applications.
11 - ARM Cortex-M4 up to 180MHz with FPU
12 - 2MB internal Flash Memory
13 - External memory support through FMC controller (PSRAM, SDRAM, NOR, NAND)
14 - I2C, SPI, SAI, CAN, USB OTG, Ethernet controllers
15 - LCD controller & Camera interface
16 - Cryptographic processor
19 ---------
23 …www.st.com/web/en/catalog/mmc/FM141/SC1169/SS1577/LN1806?ecmp=stm32f429-439_pron_pr-ces2014_nov2013
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dvf610m4-colibri.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * Device tree for Colibri VF61 Cortex-M4 support
8 /dts-v1/;
12 model = "VF610 Cortex-M4";
17 stdout-path = "serial2:115200";
47 pinctrl-names = "default";
48 pinctrl-0 = <&pinctrl_uart2>;
53 vf610-colibri {
Dvf610m4-cosmic.dts2 * Device tree for Cosmic+ VF6xx Cortex-M4 support
8 * This file is dual-licensed: you can use it either under the terms
47 /dts-v1/;
51 model = "VF610 Cortex-M4";
76 pinctrl-names = "default";
77 pinctrl-0 = <&pinctrl_uart3>;
82 vf610-cosmic {
Dlpc4350.dtsi9 * Released under the terms of 3-clause BSD License
19 compatible = "arm,cortex-m4";
25 compatible = "mmio-sram";
30 compatible = "mmio-sram";
35 compatible = "mmio-sram";
/kernel/linux/linux-5.10/arch/arm/mm/
Dproc-v7m.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-v7m.S
8 * This is the "shell" of the ARMv7-M processor support.
14 #include "proc-macros.S"
31 * - loc - location to jump to for soft reset
104 * This should be able to cover all ARMv7-M cores.
140 ldmia sp, {r0-r3, r12}
144 @ Special-purpose control register
150 stmiane sp, {r0-r6, lr} @ v7m_invalidate_l1 touches r0-r6
152 teq r8, #0 @ re-evalutae condition
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/kernel/linux/linux-4.19/arch/arm/mm/
Dproc-v7m.S2 * linux/arch/arm/mm/proc-v7m.S
11 * This is the "shell" of the ARMv7-M processor support.
17 #include "proc-macros.S"
34 * - loc - location to jump to for soft reset
107 * This should be able to cover all ARMv7-M cores.
143 ldmia sp, {r0-r3, r12}
147 @ Special-purpose control register
153 stmneia sp, {r0-r6, lr} @ v7m_invalidate_l1 touches r0-r6
155 teq r8, #0 @ re-evalutae condition
156 ldmneia sp, {r0-r6, lr}
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/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dvf610m4-cosmic.dts2 * Device tree for Cosmic+ VF6xx Cortex-M4 support
8 * This file is dual-licensed: you can use it either under the terms
47 /dts-v1/;
51 model = "VF610 Cortex-M4";
76 pinctrl-names = "default";
77 pinctrl-0 = <&pinctrl_uart3>;
82 vf610-cosmic {
Dvf610m4-colibri.dts2 * Device tree for Colibri VF61 Cortex-M4 support
6 * This file is dual-licensed: you can use it either under the terms
45 /dts-v1/;
49 model = "VF610 Cortex-M4";
54 stdout-path = "serial2:115200";
83 pinctrl-names = "default";
84 pinctrl-0 = <&pinctrl_uart2>;
89 vf610-colibri {
Dlpc4350.dtsi9 * Released under the terms of 3-clause BSD License
19 compatible = "arm,cortex-m4";
25 compatible = "mmio-sram";
30 compatible = "mmio-sram";
35 compatible = "mmio-sram";
/kernel/liteos_m/arch/arm/
DKconfig4 # ARM has 32-bit(Aarch32) and 64-bit(Aarch64) implementations
10 32-bit ARM architecture implementations, Except the M-profile.
11 It is not limited to ARMv7-A but also ARMv7-R, ARMv8-A 32-bit and etc.
24 default "armv7-m" if ARCH_ARM_V7M
33 …onal extension to the Arm, Thumb, and ThumbEE instruction sets in the ARMv7-A and ARMv7-R profiles.
34 …VFPv3U is a variant of VFPv3 that supports the trapping of floating-point exceptions to support co…
39 …onal extension to the Arm, Thumb, and ThumbEE instruction sets in the ARMv7-A and ARMv7-R profiles.
40 …VFPv4U is a variant of VFPv4 that supports the trapping of floating-point exceptions to support co…
41 …VFPv4 and VFPv4U add both the Half-precision Extension and the fused multiply-add instructions to …
47 VPU implemented with 16 doubleword registers (16 x 64-bit).
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/kernel/liteos_m/arch/arm/cortex-m4/iar/
Dlos_arch_interrupt.h2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
84 * Count of M-Core system interrupt vector.
90 * Count of M-Core interrupt vector.
113 …* The value range of the interrupt number applicable for a Cortex-M4 platform is [OS_USER_HWI_MIN,…
123 * Solution: Pass in a valid non-null hardware interrupt handling function.
153 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be…
164 * The value range of the interrupt priority applicable for a Cortex-M4 platform is [0,15].
185 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be…
203 * Interrupt Priority-Level Registers.
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/kernel/liteos_m/arch/arm/cortex-m4/gcc/
Dlos_arch_interrupt.h2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
84 * Count of M-Core system interrupt vector.
90 * Count of M-Core interrupt vector.
113 …* The value range of the interrupt number applicable for a Cortex-M4 platform is [OS_USER_HWI_MIN,…
123 * Solution: Pass in a valid non-null hardware interrupt handling function.
153 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be…
164 * The value range of the interrupt priority applicable for a Cortex-M4 platform is [0,15].
185 …* Solution: Check whether the interrupt specified by the passed-in interrupt number has already be…
203 * Interrupt Priority-Level Registers.
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/kernel/liteos_m/arch/
DBUILD.gn1 # Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved.
2 # Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved.
38 if ("$board_cpu" == "arm9" || "$board_cpu" == "cortex-m3" ||
39 "$board_cpu" == "cortex-m4" || "$board_cpu" == "cortex-m7" ||
40 "$board_cpu" == "cortex-m33" || "$board_cpu" == "cortex-m55") {
46 modules += [ "risc-v" ]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/stm32/
Dst,mlahb.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: STMicroelectronics STM32 ML-AHB interconnect bindings
10 - Fabien Dessenne <fabien.dessenne@st.com>
11 - Arnaud Pouliquen <arnaud.pouliquen@st.com>
14 These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects
15 a Cortex-M subsystem with dedicated memories. The MCU SRAM and RETRAM memory
17 using different buses (see [2]): balancing the Cortex-M firmware accesses
23 - $ref: /schemas/simple-bus.yaml#
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/freescale/
Dfsl,vf610-mscm-ir.txt1 Freescale Vybrid Miscellaneous System Control - Interrupt Router
8 which comes with a Cortex-A5/Cortex-M4 combination).
11 - compatible: "fsl,vf610-mscm-ir"
12 - reg: the register range of the MSCM Interrupt Router
13 - fsl,cpucfg: The handle to the MSCM CPU configuration node, required
15 - interrupt-controller: Identifies the node as an interrupt controller
16 - #interrupt-cells: Two cells, interrupt number and cells.
23 mscm_ir: interrupt-controller@40001800 {
24 compatible = "fsl,vf610-mscm-ir";
27 interrupt-controller;
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/kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/freescale/
Dfsl,vf610-mscm-ir.txt1 Freescale Vybrid Miscellaneous System Control - Interrupt Router
8 which comes with a Cortex-A5/Cortex-M4 combination).
11 - compatible: "fsl,vf610-mscm-ir"
12 - reg: the register range of the MSCM Interrupt Router
13 - fsl,cpucfg: The handle to the MSCM CPU configuration node, required
15 - interrupt-controller: Identifies the node as an interrupt controller
16 - #interrupt-cells: Two cells, interrupt number and cells.
23 mscm_ir: interrupt-controller@40001800 {
24 compatible = "fsl,vf610-mscm-ir";
27 interrupt-controller;
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/kernel/linux/linux-4.19/arch/arm/mach-imx/
Dmach-imx7d-cm4.c1 // SPDX-License-Identifier: GPL-2.0
11 "fsl,imx7d-cm4",
15 DT_MACHINE_START(IMX7D, "Freescale i.MX7 Dual Cortex-M4 (Device Tree)")
/kernel/linux/linux-5.10/arch/arm/mach-imx/
Dmach-imx7d-cm4.c1 // SPDX-License-Identifier: GPL-2.0
11 "fsl,imx7d-cm4",
15 DT_MACHINE_START(IMX7D, "Freescale i.MX7 Dual Cortex-M4 (Device Tree)")
/kernel/linux/linux-5.10/drivers/firmware/imx/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
18 The System Controller Firmware (SCFW) is a low-level system function
19 which runs on a dedicated Cortex-M core to provide power, clock, and
24 SCU firmware running on M4.
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/remoteproc/
Dimx-rproc.txt1 NXP iMX6SX/iMX7D Co-Processor Bindings
2 ----------------------------------------
4 This binding provides support for ARM Cortex M4 Co-processor found on some
8 - compatible Should be one of:
9 "fsl,imx7d-cm4"
10 "fsl,imx6sx-cm4"
11 - clocks Clock for co-processor (See: ../clock/clock-bindings.txt)
12 - syscon Phandle to syscon block which provide access to
16 - memory-region list of phandels to the reserved memory regions.
17 (See: ../reserved-memory/reserved-memory.txt)
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