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/kernel/linux/linux-5.10/arch/x86/include/asm/
Ddebugreg.h1 /* SPDX-License-Identifier: GPL-2.0 */
27 asm("mov %%db0, %0" :"=r" (val)); in native_get_debugreg()
42 asm("mov %%db7, %0" :"=r" (val)); in native_get_debugreg()
54 asm("mov %0, %%db0" ::"r" (value)); in native_set_debugreg()
69 asm("mov %0, %%db7" ::"r" (value)); in native_set_debugreg()
81 /* Zero-out the individual HW breakpoint address registers */ in hw_breakpoint_disable()
/kernel/linux/linux-4.19/arch/x86/include/asm/
Ddebugreg.h1 /* SPDX-License-Identifier: GPL-2.0 */
27 asm("mov %%db0, %0" :"=r" (val)); in native_get_debugreg()
42 asm("mov %%db7, %0" :"=r" (val)); in native_get_debugreg()
54 asm("mov %0, %%db0" ::"r" (value)); in native_set_debugreg()
69 asm("mov %0, %%db7" ::"r" (value)); in native_set_debugreg()
81 /* Zero-out the individual HW breakpoint address registers */ in hw_breakpoint_disable()
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/auxdisplay/
Dhit,hd44780.txt5 which can be used in either 4-bit or 8-bit mode.
8 - compatible: Must contain "hit,hd44780",
9 - data-gpios: Must contain an array of either 4 or 8 GPIO specifiers,
10 referring to the GPIO pins connected to the data signal lines DB0-DB7
11 (8-bit mode) or DB4-DB7 (4-bit mode) of the LCD Controller's bus interface,
12 - enable-gpios: Must contain a GPIO specifier, referring to the GPIO pin
15 - rs-gpios: Must contain a GPIO specifier, referring to the GPIO pin
18 - display-height-chars: Height of the display, in character cells,
19 - display-width-chars: Width of the display, in character cells.
22 - rw-gpios: Must contain a GPIO specifier, referring to the GPIO pin
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/auxdisplay/
Dhit,hd44780.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Geert Uytterhoeven <geert@linux-m68k.org>
15 interface, which can be used in either 4-bit or 8-bit mode.
21 data-gpios:
23 GPIO pins connected to the data signal lines DB0-DB7 (8-bit mode) or
24 DB4-DB7 (4-bit mode) of the LCD Controller's bus interface.
26 - maxItems: 4
27 - maxItems: 8
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/kernel/linux/linux-5.10/arch/sh/boards/mach-migor/
Dlcd_qvga.c1 // SPDX-License-Identifier: GPL-2.0
23 * is made up of a 240x320 LCD hooked up to a R61505U (or HX8347-A01?)
24 * Driver IC. This IC is connected to the SH7722 built-in LCDC using a
25 * SYS-80 interface configured in 16 bit mode.
38 /* DB0-DB7 are connected to D1-D8, and DB8-DB15 to D10-D17 */
53 sys_ops->write_index(sys_ops_handle, adjust_reg18(reg << 8 | data)); in write_reg()
60 sys_ops->write_index(sys_ops_handle, adjust_reg18(reg)); in write_reg16()
61 sys_ops->write_data(sys_ops_handle, adjust_reg18(data)); in write_reg16()
70 sys_ops->write_index(sys_ops_handle, adjust_reg18(reg)); in read_reg16()
71 data = sys_ops->read_data(sys_ops_handle); in read_reg16()
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/kernel/linux/linux-4.19/arch/sh/boards/mach-migor/
Dlcd_qvga.c26 * is made up of a 240x320 LCD hooked up to a R61505U (or HX8347-A01?)
27 * Driver IC. This IC is connected to the SH7722 built-in LCDC using a
28 * SYS-80 interface configured in 16 bit mode.
41 /* DB0-DB7 are connected to D1-D8, and DB8-DB15 to D10-D17 */
56 sys_ops->write_index(sys_ops_handle, adjust_reg18(reg << 8 | data)); in write_reg()
63 sys_ops->write_index(sys_ops_handle, adjust_reg18(reg)); in write_reg16()
64 sys_ops->write_data(sys_ops_handle, adjust_reg18(data)); in write_reg16()
73 sys_ops->write_index(sys_ops_handle, adjust_reg18(reg)); in read_reg16()
74 data = sys_ops->read_data(sys_ops_handle); in read_reg16()
126 return -ENODEV; in migor_lcd_qvga_setup()
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/kernel/linux/linux-4.19/arch/x86/include/asm/xen/
Dinterface.h2 * arch-x86_32.h
24 * Copyright (c) 2004-2006, K A Fraser
104 #define MACH2PHYS_NR_ENTRIES ((MACH2PHYS_VIRT_END-MACH2PHYS_VIRT_START)>>__MACH2PHYS_SHIFT)
106 /* Maximum number of virtual CPUs in multi-processor guests. */
114 * start of the GDT because some stupid OSes export hard-coded selector values
115 * in their ABI. These hard-coded values are always near the start of the GDT,
135 #define TI_GET_DPL(_ti) ((_ti)->flags & 3)
136 #define TI_GET_IF(_ti) ((_ti)->flags & 4)
137 #define TI_SET_DPL(_ti, _dpl) ((_ti)->flags |= (_dpl))
138 #define TI_SET_IF(_ti, _if) ((_ti)->flags |= ((!!(_if))<<2))
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/kernel/linux/linux-5.10/arch/x86/include/asm/xen/
Dinterface.h2 * arch-x86_32.h
24 * Copyright (c) 2004-2006, K A Fraser
104 #define MACH2PHYS_NR_ENTRIES ((MACH2PHYS_VIRT_END-MACH2PHYS_VIRT_START)>>__MACH2PHYS_SHIFT)
106 /* Maximum number of virtual CPUs in multi-processor guests. */
114 * start of the GDT because some stupid OSes export hard-coded selector values
115 * in their ABI. These hard-coded values are always near the start of the GDT,
135 #define TI_GET_DPL(_ti) ((_ti)->flags & 3)
136 #define TI_GET_IF(_ti) ((_ti)->flags & 4)
137 #define TI_SET_DPL(_ti, _dpl) ((_ti)->flags |= (_dpl))
138 #define TI_SET_IF(_ti, _if) ((_ti)->flags |= ((!!(_if))<<2))
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/kernel/linux/linux-4.19/include/drm/
Ddrm_dp_helper.h40 * MST: Multistream Transport - part of DP 1.2a
134 # define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */
313 * 0x80-0x8f describe downstream port capabilities, but there are two layouts
367 /* DPCD 1.1 only. For DPCD >= 1.2 see per-lane DP_LINK_QUAL_LANEn_SET */
769 /* 0-5 sink count */
908 /* peer device type - DP 1.2a Table 2-92 */
915 /* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */
932 /* DP 1.2 MST sideband nak reasons - table 2.84 */
949 /* DP 1.2 MST PORTs - Section 2.5.1 v1.2a spec */
980 #define DP_SDP_CAMERA_GENERIC(i) (0x08 + (i)) /* 0-7, DP 1.3 */
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/kernel/linux/linux-4.19/drivers/gpu/drm/i915/
Dintel_hdmi.c3 * Copyright © 2006-2009 Intel Corporation
46 return hdmi_to_dig_port(intel_hdmi)->base.base.dev; in intel_hdmi_to_dev()
58 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, in assert_hdmi_port_disabled()
75 return &intel_dig_port->hdmi; in enc_to_intel_hdmi()
80 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); in intel_attached_hdmi()
157 struct drm_device *dev = encoder->dev; in g4x_write_infoframe()
192 struct drm_i915_private *dev_priv = to_i915(encoder->dev); in g4x_infoframe_enabled()
199 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->base.port)) in g4x_infoframe_enabled()
212 struct drm_device *dev = encoder->dev; in ibx_write_infoframe()
214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); in ibx_write_infoframe()
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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
Dintel_hdmi.c3 * Copyright © 2006-2009 Intel Corporation
62 return hdmi_to_dig_port(intel_hdmi)->base.base.dev; in intel_hdmi_to_dev()
75 intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits, in assert_hdmi_port_disabled()
83 drm_WARN(&dev_priv->drm, in assert_hdmi_transcoder_func_disabled()
92 container_of(&encoder->base, struct intel_digital_port, in enc_to_intel_hdmi()
94 return &dig_port->hdmi; in enc_to_intel_hdmi()
218 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in g4x_write_infoframe()
222 drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), in g4x_write_infoframe()
253 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in g4x_read_infoframe()
271 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in g4x_infoframes_enabled()
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/kernel/linux/linux-5.10/drivers/scsi/
DFlashPoint.c3 FlashPoint.c -- FlashPoint SCCB Manager for Linux
11 Copyright 1995-1996 by Mylex Corporation. All Rights Reserved
14 and a BSD-style copyright; see LICENSE.FlashPoint for details.
229 unsigned char niSysConf; /* Adapter Configuration byte -
231 unsigned char niScsiConf; /* SCSI Configuration byte -
233 unsigned char niScamConf; /* SCAM Configuration byte -
235 unsigned char niAdapId; /* Host Adapter ID -
276 #define TYPE_CODE0 0x63 /*Level2 Mstr (bits 7-6), */
278 #define SLV_TYPE_CODE0 0xA3 /*Priority Bit set (bits 7-6), */
437 #define XFER_HOST_DMA 0x00 /* 0 0 0 Transfer Host -> DMA */
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/kernel/linux/linux-4.19/drivers/scsi/
DFlashPoint.c3 FlashPoint.c -- FlashPoint SCCB Manager for Linux
11 Copyright 1995-1996 by Mylex Corporation. All Rights Reserved
14 and a BSD-style copyright; see LICENSE.FlashPoint for details.
229 unsigned char niSysConf; /* Adapter Configuration byte -
231 unsigned char niScsiConf; /* SCSI Configuration byte -
233 unsigned char niScamConf; /* SCAM Configuration byte -
235 unsigned char niAdapId; /* Host Adapter ID -
276 #define TYPE_CODE0 0x63 /*Level2 Mstr (bits 7-6), */
278 #define SLV_TYPE_CODE0 0xA3 /*Priority Bit set (bits 7-6), */
437 #define XFER_HOST_DMA 0x00 /* 0 0 0 Transfer Host -> DMA */
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