| /kernel/linux/linux-5.10/drivers/clk/baikal-t1/ |
| D | ccu-div.c | 12 #define pr_fmt(fmt) "bt1-ccu-div: " fmt
27 #include "ccu-div.h"
61 unsigned long div) in ccu_div_lock_delay_ns() argument
63 u64 ns = 4ULL * (div ?: 1) * NSEC_PER_SEC; in ccu_div_lock_delay_ns()
71 unsigned long div) in ccu_div_calc_freq() argument
73 return ref_clk / (div ?: 1); in ccu_div_calc_freq()
76 static int ccu_div_var_update_clkdiv(struct ccu_div *div, in ccu_div_var_update_clkdiv() argument
87 if (div->features & CCU_DIV_LOCK_SHIFTED) in ccu_div_var_update_clkdiv()
92 regmap_update_bits(div->sys_regs, div->reg_ctl, in ccu_div_var_update_clkdiv()
102 regmap_read(div->sys_regs, div->reg_ctl, &val); in ccu_div_var_update_clkdiv()
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| /kernel/linux/linux-4.19/drivers/clk/ti/ |
| D | divider.c | 36 for (clkt = table; clkt->div; clkt++) in _get_table_maxdiv()
37 if (clkt->div > maxdiv) in _get_table_maxdiv()
38 maxdiv = clkt->div; in _get_table_maxdiv()
58 for (clkt = table; clkt->div; clkt++) in _get_table_div()
60 return clkt->div; in _get_table_div()
76 unsigned int div) in _get_table_val() argument
80 for (clkt = table; clkt->div; clkt++) in _get_table_val()
81 if (clkt->div == div) in _get_table_val()
86 static unsigned int _get_val(struct clk_omap_divider *divider, u8 div) in _get_val() argument
89 return div; in _get_val()
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| /kernel/linux/linux-5.10/drivers/clk/berlin/ |
| D | berlin2-div.c | 16 #include "berlin2-div.h"
36 * (D) constant div-by-3 clock divider
38 * (F) constant div-by-3 clock mux controlled by <D3Switch>
46 * Also, clock gate and pll mux is not available on every div cell, so
67 struct berlin2_div *div = to_berlin2_div(hw); in berlin2_div_is_enabled() local
68 struct berlin2_div_map *map = &div->map; in berlin2_div_is_enabled()
71 if (div->lock) in berlin2_div_is_enabled()
72 spin_lock(div->lock); in berlin2_div_is_enabled()
74 reg = readl_relaxed(div->base + map->gate_offs); in berlin2_div_is_enabled()
77 if (div->lock) in berlin2_div_is_enabled()
[all …]
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| /kernel/linux/linux-4.19/drivers/clk/berlin/ |
| D | berlin2-div.c | 15 #include "berlin2-div.h"
35 * (D) constant div-by-3 clock divider
37 * (F) constant div-by-3 clock mux controlled by <D3Switch>
45 * Also, clock gate and pll mux is not available on every div cell, so
66 struct berlin2_div *div = to_berlin2_div(hw); in berlin2_div_is_enabled() local
67 struct berlin2_div_map *map = &div->map; in berlin2_div_is_enabled()
70 if (div->lock) in berlin2_div_is_enabled()
71 spin_lock(div->lock); in berlin2_div_is_enabled()
73 reg = readl_relaxed(div->base + map->gate_offs); in berlin2_div_is_enabled()
76 if (div->lock) in berlin2_div_is_enabled()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/ |
| D | clk-divider.c | 50 for (clkt = table; clkt->div; clkt++) in _get_table_maxdiv()
51 if (clkt->div > maxdiv && clkt->val <= mask) in _get_table_maxdiv()
52 maxdiv = clkt->div; in _get_table_maxdiv()
61 for (clkt = table; clkt->div; clkt++) in _get_table_mindiv()
62 if (clkt->div < mindiv) in _get_table_mindiv()
63 mindiv = clkt->div; in _get_table_mindiv()
84 for (clkt = table; clkt->div; clkt++) in _get_table_div()
86 return clkt->div; in _get_table_div()
105 unsigned int div) in _get_table_val() argument
109 for (clkt = table; clkt->div; clkt++) in _get_table_val()
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| D | clk-milbeaut.c | 83 u8 div; member
101 { .val = 0, .div = 8 },
102 { .val = 1, .div = 9 },
103 { .val = 2, .div = 10 },
104 { .val = 3, .div = 15 },
105 { .div = 0 },
109 { .val = 1, .div = 2 },
110 { .val = 3, .div = 4 },
111 { .div = 0 },
115 { .val = 3, .div = 4 },
[all …]
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| D | clk-cdce706.c | 29 #define CDCE706_DIVIDER(div) (13 + (div)) argument
50 #define CDCE706_DIVIDER_PLL(div) (9 + (div) - ((div) > 2) - ((div) > 4)) argument
51 #define CDCE706_DIVIDER_PLL_SHIFT(div) ((div) < 2 ? 5 : 3 * ((div) & 1)) argument
52 #define CDCE706_DIVIDER_PLL_MASK(div) (0x7 << CDCE706_DIVIDER_PLL_SHIFT(div)) argument
72 unsigned div; member
168 "%s, pll: %d, mux: %d, mul: %u, div: %u\n", in cdce706_pll_recalc_rate()
169 __func__, hwd->idx, hwd->mux, hwd->mul, hwd->div); in cdce706_pll_recalc_rate()
172 if (hwd->div && hwd->mul) { in cdce706_pll_recalc_rate()
175 do_div(res, hwd->div); in cdce706_pll_recalc_rate()
179 if (hwd->div) in cdce706_pll_recalc_rate()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/imx/ |
| D | clk-divider-gate.c | 21 struct clk_divider *div = to_clk_divider(hw); in to_clk_divider_gate() local
23 return container_of(div, struct clk_divider_gate, divider); in to_clk_divider_gate()
29 struct clk_divider *div = to_clk_divider(hw); in clk_divider_gate_recalc_rate_ro() local
32 val = readl(div->reg) >> div->shift; in clk_divider_gate_recalc_rate_ro()
33 val &= clk_div_mask(div->width); in clk_divider_gate_recalc_rate_ro()
37 return divider_recalc_rate(hw, parent_rate, val, div->table, in clk_divider_gate_recalc_rate_ro()
38 div->flags, div->width); in clk_divider_gate_recalc_rate_ro()
45 struct clk_divider *div = to_clk_divider(hw); in clk_divider_gate_recalc_rate() local
49 spin_lock_irqsave(div->lock, flags); in clk_divider_gate_recalc_rate()
54 val = readl(div->reg) >> div->shift; in clk_divider_gate_recalc_rate()
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/ti/ |
| D | divider.c | 34 for (clkt = table; clkt->div; clkt++) in _get_table_div()
36 return clkt->div; in _get_table_div()
49 for (clkt = divider->table; clkt->div; clkt++) in _setup_mask()
80 unsigned int div) in _get_table_val() argument
84 for (clkt = table; clkt->div; clkt++) in _get_table_val()
85 if (clkt->div == div) in _get_table_val()
90 static unsigned int _get_val(struct clk_omap_divider *divider, u8 div) in _get_val() argument
93 return div; in _get_val()
95 return __ffs(div); in _get_val()
97 return _get_table_val(divider->table, div); in _get_val()
[all …]
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| /kernel/linux/linux-4.19/drivers/clk/ |
| D | clk-divider.c | 37 for (clkt = table; clkt->div; clkt++) in _get_table_maxdiv()
38 if (clkt->div > maxdiv && clkt->val <= mask) in _get_table_maxdiv()
39 maxdiv = clkt->div; in _get_table_maxdiv()
48 for (clkt = table; clkt->div; clkt++) in _get_table_mindiv()
49 if (clkt->div < mindiv) in _get_table_mindiv()
50 mindiv = clkt->div; in _get_table_mindiv()
71 for (clkt = table; clkt->div; clkt++) in _get_table_div()
73 return clkt->div; in _get_table_div()
92 unsigned int div) in _get_table_val() argument
96 for (clkt = table; clkt->div; clkt++) in _get_table_val()
[all …]
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| D | clk-cdce706.c | 32 #define CDCE706_DIVIDER(div) (13 + (div)) argument
53 #define CDCE706_DIVIDER_PLL(div) (9 + (div) - ((div) > 2) - ((div) > 4)) argument
54 #define CDCE706_DIVIDER_PLL_SHIFT(div) ((div) < 2 ? 5 : 3 * ((div) & 1)) argument
55 #define CDCE706_DIVIDER_PLL_MASK(div) (0x7 << CDCE706_DIVIDER_PLL_SHIFT(div)) argument
75 unsigned div; member
171 "%s, pll: %d, mux: %d, mul: %u, div: %u\n", in cdce706_pll_recalc_rate()
172 __func__, hwd->idx, hwd->mux, hwd->mul, hwd->div); in cdce706_pll_recalc_rate()
175 if (hwd->div && hwd->mul) { in cdce706_pll_recalc_rate()
178 do_div(res, hwd->div); in cdce706_pll_recalc_rate()
182 if (hwd->div) in cdce706_pll_recalc_rate()
[all …]
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| /kernel/linux/linux-4.19/drivers/clk/mxs/ |
| D | clk-div.c | 44 struct clk_div *div = to_clk_div(hw); in clk_div_recalc_rate() local
46 return div->ops->recalc_rate(&div->divider.hw, parent_rate); in clk_div_recalc_rate()
52 struct clk_div *div = to_clk_div(hw); in clk_div_round_rate() local
54 return div->ops->round_rate(&div->divider.hw, rate, prate); in clk_div_round_rate()
60 struct clk_div *div = to_clk_div(hw); in clk_div_set_rate() local
63 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); in clk_div_set_rate()
65 ret = mxs_clk_wait(div->reg, div->busy); in clk_div_set_rate()
79 struct clk_div *div; in mxs_clk_div() local
83 div = kzalloc(sizeof(*div), GFP_KERNEL); in mxs_clk_div()
84 if (!div) in mxs_clk_div()
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| /kernel/linux/linux-5.10/drivers/clk/mxs/ |
| D | clk-div.c | 38 struct clk_div *div = to_clk_div(hw); in clk_div_recalc_rate() local
40 return div->ops->recalc_rate(&div->divider.hw, parent_rate); in clk_div_recalc_rate()
46 struct clk_div *div = to_clk_div(hw); in clk_div_round_rate() local
48 return div->ops->round_rate(&div->divider.hw, rate, prate); in clk_div_round_rate()
54 struct clk_div *div = to_clk_div(hw); in clk_div_set_rate() local
57 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); in clk_div_set_rate()
59 ret = mxs_clk_wait(div->reg, div->busy); in clk_div_set_rate()
73 struct clk_div *div; in mxs_clk_div() local
77 div = kzalloc(sizeof(*div), GFP_KERNEL); in mxs_clk_div()
78 if (!div) in mxs_clk_div()
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| /kernel/linux/linux-4.19/drivers/clk/bcm/ |
| D | clk-iproc-asiu.c | 32 struct iproc_asiu_div div; member
92 val = readl(asiu->div_base + clk->div.offset); in iproc_asiu_clk_recalc_rate()
93 if ((val & (1 << clk->div.en_shift)) == 0) { in iproc_asiu_clk_recalc_rate()
99 div_h = (val >> clk->div.high_shift) & bit_mask(clk->div.high_width); in iproc_asiu_clk_recalc_rate()
101 div_l = (val >> clk->div.low_shift) & bit_mask(clk->div.low_width); in iproc_asiu_clk_recalc_rate()
114 unsigned int div; in iproc_asiu_clk_round_rate() local
122 div = DIV_ROUND_UP(*parent_rate, rate); in iproc_asiu_clk_round_rate()
123 if (div < 2) in iproc_asiu_clk_round_rate()
126 return *parent_rate / div; in iproc_asiu_clk_round_rate()
134 unsigned int div, div_h, div_l; in iproc_asiu_clk_set_rate() local
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/bcm/ |
| D | clk-iproc-asiu.c | 32 struct iproc_asiu_div div; member
92 val = readl(asiu->div_base + clk->div.offset); in iproc_asiu_clk_recalc_rate()
93 if ((val & (1 << clk->div.en_shift)) == 0) { in iproc_asiu_clk_recalc_rate()
99 div_h = (val >> clk->div.high_shift) & bit_mask(clk->div.high_width); in iproc_asiu_clk_recalc_rate()
101 div_l = (val >> clk->div.low_shift) & bit_mask(clk->div.low_width); in iproc_asiu_clk_recalc_rate()
114 unsigned int div; in iproc_asiu_clk_round_rate() local
122 div = DIV_ROUND_CLOSEST(*parent_rate, rate); in iproc_asiu_clk_round_rate()
123 if (div < 2) in iproc_asiu_clk_round_rate()
126 return *parent_rate / div; in iproc_asiu_clk_round_rate()
134 unsigned int div, div_h, div_l; in iproc_asiu_clk_set_rate() local
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/meson/ |
| D | clk-regmap.c | 63 struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk); in clk_regmap_div_recalc_rate() local
67 ret = regmap_read(clk->map, div->offset, &val); in clk_regmap_div_recalc_rate()
72 val >>= div->shift; in clk_regmap_div_recalc_rate()
73 val &= clk_div_mask(div->width); in clk_regmap_div_recalc_rate()
74 return divider_recalc_rate(hw, prate, val, div->table, div->flags, in clk_regmap_div_recalc_rate()
75 div->width); in clk_regmap_div_recalc_rate()
82 struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk); in clk_regmap_div_round_rate() local
87 if (div->flags & CLK_DIVIDER_READ_ONLY) { in clk_regmap_div_round_rate()
88 ret = regmap_read(clk->map, div->offset, &val); in clk_regmap_div_round_rate()
93 val >>= div->shift; in clk_regmap_div_round_rate()
[all …]
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| /kernel/linux/linux-4.19/drivers/clk/meson/ |
| D | clk-regmap.c | 57 struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk); in clk_regmap_div_recalc_rate() local
61 ret = regmap_read(clk->map, div->offset, &val); in clk_regmap_div_recalc_rate()
66 val >>= div->shift; in clk_regmap_div_recalc_rate()
67 val &= clk_div_mask(div->width); in clk_regmap_div_recalc_rate()
68 return divider_recalc_rate(hw, prate, val, div->table, div->flags, in clk_regmap_div_recalc_rate()
69 div->width); in clk_regmap_div_recalc_rate()
76 struct clk_regmap_div_data *div = clk_get_regmap_div_data(clk); in clk_regmap_div_round_rate() local
81 if (div->flags & CLK_DIVIDER_READ_ONLY) { in clk_regmap_div_round_rate()
82 ret = regmap_read(clk->map, div->offset, &val); in clk_regmap_div_round_rate()
87 val >>= div->shift; in clk_regmap_div_round_rate()
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| /kernel/linux/linux-5.10/drivers/clk/sunxi/ |
| D | clk-sunxi.c | 35 u8 div; in sun4i_get_pll1_factors() local
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
52 if (div < 10) in sun4i_get_pll1_factors()
56 else if (div < 20 || (div < 32 && (div & 1))) in sun4i_get_pll1_factors()
61 else if (div < 40 || (div < 64 && (div & 2))) in sun4i_get_pll1_factors()
69 div <<= req->p; in sun4i_get_pll1_factors()
70 div /= (req->k + 1); in sun4i_get_pll1_factors()
71 req->n = div / 4; in sun4i_get_pll1_factors()
159 u8 div; in sun8i_a23_get_pll1_factors() local
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| /kernel/linux/linux-4.19/drivers/clk/sunxi/ |
| D | clk-sunxi.c | 43 u8 div; in sun4i_get_pll1_factors() local
46 div = req->rate / 6000000; in sun4i_get_pll1_factors()
47 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
60 if (div < 10) in sun4i_get_pll1_factors()
64 else if (div < 20 || (div < 32 && (div & 1))) in sun4i_get_pll1_factors()
69 else if (div < 40 || (div < 64 && (div & 2))) in sun4i_get_pll1_factors()
77 div <<= req->p; in sun4i_get_pll1_factors()
78 div /= (req->k + 1); in sun4i_get_pll1_factors()
79 req->n = div / 4; in sun4i_get_pll1_factors()
167 u8 div; in sun8i_a23_get_pll1_factors() local
[all …]
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| /kernel/linux/linux-5.10/drivers/mmc/host/ |
| D | meson-mx-sdhc-clkc.c | 19 struct clk_divider div; member
34 { .div = 6, .val = 5, },
35 { .div = 8, .val = 7, },
36 { .div = 9, .val = 8, },
37 { .div = 10, .val = 9, },
38 { .div = 12, .val = 11, },
39 { .div = 16, .val = 15, },
40 { .div = 18, .val = 17, },
41 { .div = 34, .val = 33, },
42 { .div = 142, .val = 141, },
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/tegra/ |
| D | clk-divider.c | 24 int div; in get_div() local
26 div = div_frac_get(rate, parent_rate, divider->width, in get_div()
29 if (div < 0) in get_div()
32 return div; in get_div()
40 int div, mul; in clk_frac_div_recalc_rate() local
49 div = (reg >> divider->shift) & div_mask(divider); in clk_frac_div_recalc_rate()
52 div += mul; in clk_frac_div_recalc_rate()
55 rate += div - 1; in clk_frac_div_recalc_rate()
56 do_div(rate, div); in clk_frac_div_recalc_rate()
65 int div, mul; in clk_frac_div_round_rate() local
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/ingenic/ |
| D | cgu.c | 371 u32 div_reg, div; in ingenic_clk_recalc_rate() local
374 div_reg = readl(cgu->base + clk_info->div.reg); in ingenic_clk_recalc_rate()
375 div = (div_reg >> clk_info->div.shift) & in ingenic_clk_recalc_rate()
376 GENMASK(clk_info->div.bits - 1, 0); in ingenic_clk_recalc_rate()
378 if (clk_info->div.div_table) in ingenic_clk_recalc_rate()
379 div = clk_info->div.div_table[div]; in ingenic_clk_recalc_rate()
381 div = (div + 1) * clk_info->div.div; in ingenic_clk_recalc_rate()
383 rate /= div; in ingenic_clk_recalc_rate()
385 rate /= clk_info->fixdiv.div; in ingenic_clk_recalc_rate()
393 unsigned int div) in ingenic_clk_calc_hw_div() argument
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| /kernel/linux/linux-5.10/drivers/clk/sprd/ |
| D | div.c | 10 #include "div.h"
13 const struct sprd_div_internal *div, in sprd_div_helper_round_rate() argument
18 NULL, div->width, 0); in sprd_div_helper_round_rate()
27 return sprd_div_helper_round_rate(&cd->common, &cd->div, in sprd_div_round_rate()
32 const struct sprd_div_internal *div, in sprd_div_helper_recalc_rate() argument
39 val = reg >> div->shift; in sprd_div_helper_recalc_rate()
40 val &= (1 << div->width) - 1; in sprd_div_helper_recalc_rate()
43 div->width); in sprd_div_helper_recalc_rate()
52 return sprd_div_helper_recalc_rate(&cd->common, &cd->div, parent_rate); in sprd_div_recalc_rate()
56 const struct sprd_div_internal *div, in sprd_div_helper_set_rate() argument
[all …]
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| /kernel/linux/linux-4.19/drivers/clk/sprd/ |
| D | div.c | 10 #include "div.h"
13 const struct sprd_div_internal *div, in sprd_div_helper_round_rate() argument
18 NULL, div->width, 0); in sprd_div_helper_round_rate()
27 return sprd_div_helper_round_rate(&cd->common, &cd->div, in sprd_div_round_rate()
32 const struct sprd_div_internal *div, in sprd_div_helper_recalc_rate() argument
39 val = reg >> div->shift; in sprd_div_helper_recalc_rate()
40 val &= (1 << div->width) - 1; in sprd_div_helper_recalc_rate()
43 div->width); in sprd_div_helper_recalc_rate()
52 return sprd_div_helper_recalc_rate(&cd->common, &cd->div, parent_rate); in sprd_div_recalc_rate()
56 const struct sprd_div_internal *div, in sprd_div_helper_set_rate() argument
[all …]
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| /kernel/linux/linux-4.19/drivers/clk/tegra/ |
| D | clk-divider.c | 35 int div; in get_div() local
37 div = div_frac_get(rate, parent_rate, divider->width, in get_div()
40 if (div < 0) in get_div()
43 return div; in get_div()
51 int div, mul; in clk_frac_div_recalc_rate() local
55 div = reg & div_mask(divider); in clk_frac_div_recalc_rate()
58 div += mul; in clk_frac_div_recalc_rate()
61 rate += div - 1; in clk_frac_div_recalc_rate()
62 do_div(rate, div); in clk_frac_div_recalc_rate()
71 int div, mul; in clk_frac_div_round_rate() local
[all …]
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