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/kernel/linux/linux-5.10/scripts/coccinelle/misc/
Darray_size_dup.cocci28 expression as.E1, as.E2, E3;
34 ... when != \(subE1\|subE2\) aop E3
57 expression as.E1, as.E2, E3;
63 ... when != \(subE1\|subE2\) aop E3
84 expression E1, E2, E3;
87 array3_size(E1, E2, E3)
92 expression subE3 <= as3.E3;
93 expression as3.E1, as3.E2, as3.E3, E4;
98 * E1 * E2 * E3@p1
101 * array3_size(E1, E2, E3)@p2
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/kernel/linux/linux-4.19/scripts/coccinelle/api/alloc/
Dzalloc-simple.cocci49 expression E1,E2,E3,E4;
72 - x = dma_alloc_coherent(E2,E1,E3,E4);
73 + x = dma_zalloc_coherent(E2,E1,E3,E4);
75 - x = (T *)dma_alloc_coherent(E2,E1,E3,E4);
76 + x = dma_zalloc_coherent(E2,E1,E3,E4);
78 - x = (T)dma_alloc_coherent(E2,E1,E3,E4);
79 + x = (T)dma_zalloc_coherent(E2,E1,E3,E4);
81 - x = kmalloc_node(E1,E2,E3);
82 + x = kzalloc_node(E1,E2,E3);
84 - x = (T *)kmalloc_node(E1,E2,E3);
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/kernel/linux/linux-5.10/scripts/coccinelle/api/alloc/
Dzalloc-simple.cocci50 expression E1,E2,E3,E4;
73 - x = kmalloc_node(E1,E2,E3);
74 + x = kzalloc_node(E1,E2,E3);
76 - x = (T *)kmalloc_node(E1,E2,E3);
77 + x = kzalloc_node(E1,E2,E3);
79 - x = (T)kmalloc_node(E1,E2,E3);
80 + x = (T)kzalloc_node(E1,E2,E3);
82 - x = kmem_cache_alloc(E3,E4);
83 + x = kmem_cache_zalloc(E3,E4);
85 - x = (T *)kmem_cache_alloc(E3,E4);
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/kernel/linux/linux-5.10/scripts/coccinelle/api/
Dkstrdup.cocci32 expression flag,E1,E2,E3;
42 ... when != \(x = E3 \| from = E3 \| to = E3 \)
62 expression flag,E1,E2,E3;
72 ... when != \(x = E3 \| from = E3 \| to = E3 \)
/kernel/linux/linux-4.19/scripts/coccinelle/api/
Dkstrdup.cocci31 expression flag,E1,E2,E3;
41 ... when != \(x = E3 \| from = E3 \| to = E3 \)
61 expression flag,E1,E2,E3;
71 ... when != \(x = E3 \| from = E3 \| to = E3 \)
/kernel/linux/linux-5.10/arch/mips/include/asm/txx9/
Dtx3927.h58 #define endian_def_sb2(e1, e2, e3) \ argument
59 volatile unsigned short e1;volatile unsigned char e2, e3
60 #define endian_def_b2s(e1, e2, e3) \ argument
61 volatile unsigned char e1, e2;volatile unsigned short e3
62 #define endian_def_b4(e1, e2, e3, e4) \ argument
63 volatile unsigned char e1, e2, e3, e4
67 #define endian_def_sb2(e1, e2, e3) \ argument
68 volatile unsigned char e3, e2;volatile unsigned short e1
69 #define endian_def_b2s(e1, e2, e3) \ argument
70 volatile unsigned short e3;volatile unsigned char e2, e1
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/kernel/linux/linux-4.19/arch/mips/include/asm/txx9/
Dtx3927.h58 #define endian_def_sb2(e1, e2, e3) \ argument
59 volatile unsigned short e1;volatile unsigned char e2, e3
60 #define endian_def_b2s(e1, e2, e3) \ argument
61 volatile unsigned char e1, e2;volatile unsigned short e3
62 #define endian_def_b4(e1, e2, e3, e4) \ argument
63 volatile unsigned char e1, e2, e3, e4
67 #define endian_def_sb2(e1, e2, e3) \ argument
68 volatile unsigned char e3, e2;volatile unsigned short e1
69 #define endian_def_b2s(e1, e2, e3) \ argument
70 volatile unsigned short e3;volatile unsigned char e2, e1
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/kernel/linux/linux-4.19/drivers/edac/
Die31200_edac.c2 * Intel E3-1200
5 * Support for the E3-1200 processor family. Heavily based on previous
13 * 0108: Xeon E3-1200 Processor Family DRAM Controller
14 * 010c: Xeon E3-1200/2nd Generation Core Processor Family DRAM Controller
15 * 0150: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
16 * 0158: Xeon E3-1200 v2/Ivy Bridge DRAM Controller
17 * 015c: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
18 * 0c04: Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller
19 * 0c08: Xeon E3-1200 v3 Processor DRAM Controller
20 * 1918: Xeon E3-1200 v5 Skylake Host Bridge/DRAM Registers
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/kernel/linux/linux-5.10/drivers/edac/
Die31200_edac.c3 * Intel E3-1200
6 * Support for the E3-1200 processor family. Heavily based on previous
14 * 0108: Xeon E3-1200 Processor Family DRAM Controller
15 * 010c: Xeon E3-1200/2nd Generation Core Processor Family DRAM Controller
16 * 0150: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
17 * 0158: Xeon E3-1200 v2/Ivy Bridge DRAM Controller
18 * 015c: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
19 * 0c04: Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller
20 * 0c08: Xeon E3-1200 v3 Processor DRAM Controller
21 * 1918: Xeon E3-1200 v5 Skylake Host Bridge/DRAM Registers
[all …]
/kernel/linux/linux-5.10/arch/m68k/fpsp040/
Dx_ovfl.S77 btstb #E3,E_BYTE(%a6)
107 btstb #E3,E_BYTE(%a6)
124 bclrb #E3,E_BYTE(%a6) |test and clear E3 bit
156 btstb #E3,E_BYTE(%a6) |test E3 bit
Dx_unfl.S61 btstb #E3,E_BYTE(%a6)
95 btstb #E3,E_BYTE(%a6)
116 bclrb #E3,E_BYTE(%a6)
151 | If the exception bit set is E3, the exceptional operand from the
154 btstb #E3,E_BYTE(%a6)
Dgen_except.S168 | exception is to set the E1/E3 byte and clr the U flag.
170 | operr, and dz. commonE3 does this for E3 exceptions, which
182 bsetb #E3,E_BYTE(%a6) |set E3 flag
190 bsetb #E3,E_BYTE(%a6) |set E3 flag
300 bsetb #E3,E_BYTE(%a6) |set E3 flag
Dskeleton.S84 | The provided code will clear the E3 exception (if pending),
145 bclrb #E3,E_BYTE(%a6) |clear and test E3 flag
182 bclrb #E3,E_BYTE(%a6) |clear and test E3 flag
208 bclrb #E3,E_BYTE(%a6) |clear and test E3 flag
/kernel/linux/linux-4.19/arch/m68k/fpsp040/
Dx_ovfl.S77 btstb #E3,E_BYTE(%a6)
107 btstb #E3,E_BYTE(%a6)
124 bclrb #E3,E_BYTE(%a6) |test and clear E3 bit
156 btstb #E3,E_BYTE(%a6) |test E3 bit
Dx_unfl.S61 btstb #E3,E_BYTE(%a6)
95 btstb #E3,E_BYTE(%a6)
116 bclrb #E3,E_BYTE(%a6)
151 | If the exception bit set is E3, the exceptional operand from the
154 btstb #E3,E_BYTE(%a6)
Dgen_except.S168 | exception is to set the E1/E3 byte and clr the U flag.
170 | operr, and dz. commonE3 does this for E3 exceptions, which
182 bsetb #E3,E_BYTE(%a6) |set E3 flag
190 bsetb #E3,E_BYTE(%a6) |set E3 flag
300 bsetb #E3,E_BYTE(%a6) |set E3 flag
Dskeleton.S84 | The provided code will clear the E3 exception (if pending),
145 bclrb #E3,E_BYTE(%a6) |clear and test E3 flag
182 bclrb #E3,E_BYTE(%a6) |clear and test E3 flag
208 bclrb #E3,E_BYTE(%a6) |clear and test E3 flag
/kernel/liteos_a/testsuites/unittest/libc/time/clock/full/
Dclock_test_010.cpp77 (void)SleepTest(40e3); // 40us in ClockTestThread()
78 (void)SleepTest(50e3); // 50us in ClockTestThread()
79 (void)SleepTest(50e3 + 1); // 50us+1ns in ClockTestThread()
80 (void)SleepTest(60e3); // 60us in ClockTestThread()
81 (void)SleepTest(65e3); // 65us in ClockTestThread()
/kernel/linux/linux-5.10/Documentation/input/
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6 …<polyline transform="translate(-18.5,-16.294)" points="3e3 4800 3e3 6525 3600 7125 3600 7800" fill…
/kernel/linux/linux-4.19/Documentation/input/
Dshape.svg9 …<polyline transform="translate(-121.88 -68.4)" points="3600 3600 3e3 3600" fill="none" stroke="#00…
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/kernel/linux/linux-5.10/arch/mips/bcm47xx/
Dboard.c235 const struct bcm47xx_board_type_list3 *e3; in bcm47xx_board_get_nvram() local
302 for (e3 = bcm47xx_board_list_board; e3->value1; e3++) { in bcm47xx_board_get_nvram()
303 if (!strcmp(buf1, e3->value1) && in bcm47xx_board_get_nvram()
304 !strcmp(buf2, e3->value2) && in bcm47xx_board_get_nvram()
305 !strcmp(buf3, e3->value3)) in bcm47xx_board_get_nvram()
306 return &e3->board; in bcm47xx_board_get_nvram()
/kernel/linux/linux-4.19/arch/mips/bcm47xx/
Dboard.c234 const struct bcm47xx_board_type_list3 *e3; in bcm47xx_board_get_nvram() local
301 for (e3 = bcm47xx_board_list_board; e3->value1; e3++) { in bcm47xx_board_get_nvram()
302 if (!strcmp(buf1, e3->value1) && in bcm47xx_board_get_nvram()
303 !strcmp(buf2, e3->value2) && in bcm47xx_board_get_nvram()
304 !strcmp(buf3, e3->value3)) in bcm47xx_board_get_nvram()
305 return &e3->board; in bcm47xx_board_get_nvram()
/kernel/linux/linux-5.10/lib/
Dlocking-selftest.c275 static void name##_123(void) { E1(); E2(); E3(); } \
276 static void name##_132(void) { E1(); E3(); E2(); } \
277 static void name##_213(void) { E2(); E1(); E3(); } \
278 static void name##_231(void) { E2(); E3(); E1(); } \
279 static void name##_312(void) { E3(); E1(); E2(); } \
280 static void name##_321(void) { E3(); E2(); E1(); }
896 #define E3() \ macro
926 #undef E3
945 #define E3() \ macro
974 #undef E3
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