| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | host-generic-pci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/host-generic-pci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
13 Firmware-initialised PCI host controllers and PCI emulations, such as the
14 virtio-pci implementations found in kvmtool and other para-virtualised
21 Configuration Space is assumed to be memory-mapped (as opposed to being
26 For CAM, this 24-bit offset is:
31 While ECAM extends this by 4 bits to accommodate 4k of function space:
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| D | pcie-al.txt | 3 Amazon's Annapurna Labs PCIe Host Controller is based on the Synopsys DesignWare
5 Documentation/devicetree/bindings/pci/designware-pcie.txt.
9 - compatible:
13 - "amazon,al-alpine-v2-pcie" for alpine_v2
14 - "amazon,al-alpine-v3-pcie" for alpine_v3
16 - reg:
18 Value type: <prop-encoded-array>
19 Definition: Register ranges as listed in the reg-names property
21 - reg-names:
25 - "config" PCIe ECAM space
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/pci/ |
| D | hisilicon-pcie.txt | 3 HiSilicon PCIe host controller is based on the Synopsys DesignWare PCI core.
6 Documentation/devicetree/bindings/pci/designware-pcie.txt.
11 - compatible: Should contain "hisilicon,hip05-pcie" or "hisilicon,hip06-pcie".
12 - reg: Should contain rc_dbi, config registers location and length.
13 - reg-names: Must include the following entries:
16 - msi-parent: Should be its_pcie which is an ITS receiving MSI interrupts.
17 - port-id: Should be 0, 1, 2 or 3.
20 - status: Either "ok" or "disabled".
21 - dma-coherent: Present if DMA operations are coherent.
25 compatible = "hisilicon,hip05-pcie", "snps,dw-pcie";
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| D | pci-thunder-ecam.txt | 1 * ThunderX PCI host controller for pass-1.x silicon
3 Firmware-initialized PCI host controller to on-chip devices found on
4 some Cavium ThunderX processors. These devices have ECAM-based config
10 host-generic-pci.txt except as listed below.
13 host-generic-pci.txt:
15 - compatible : Must be "cavium,pci-host-thunder-ecam"
20 compatible = "cavium,pci-host-thunder-ecam";
22 msi-parent = <&its>;
23 msi-map = <0 &its 0x30000 0x10000>;
24 bus-range = <0 31>;
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| /kernel/linux/linux-4.19/include/linux/ |
| D | pci-ecam.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
26 * use ECAM.
34 void __iomem *win; /* 64-bit single mapping */
35 void __iomem **winp; /* 32-bit per-bus mapping */
37 struct device *parent;/* ECAM res was from this dev */
46 /* map_bus when ->sysdata is an instance of pci_config_window */
49 /* default ECAM ops */
53 extern struct pci_ecam_ops pci_32b_ops; /* 32-bit accesses only */
57 extern struct pci_ecam_ops xgene_v1_pcie_ecam_ops; /* APM X-Gene PCIe v1 */
58 extern struct pci_ecam_ops xgene_v2_pcie_ecam_ops; /* APM X-Gene PCIe v2.x */
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| /kernel/linux/linux-5.10/include/linux/ |
| D | pci-ecam.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
26 * use ECAM.
34 void __iomem *win; /* 64-bit single mapping */
35 void __iomem **winp; /* 32-bit per-bus mapping */
37 struct device *parent;/* ECAM res was from this dev */
46 /* map_bus when ->sysdata is an instance of pci_config_window */
49 /* default ECAM ops */
53 extern const struct pci_ecam_ops pci_32b_ops; /* 32-bit accesses only */
54 extern const struct pci_ecam_ops pci_32b_read_ops; /* 32-bit read only */
58 extern const struct pci_ecam_ops xgene_v1_pcie_ecam_ops; /* APM X-Gene PCIe v1 */
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| /kernel/linux/linux-5.10/drivers/pci/controller/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
50 bool "Renesas R-Car Gen2 Internal PCI controller"
54 Say Y here if you want internal PCI support on R-Car Gen2 SoC.
56 built-in EHCI/OHCI host controller present on each one.
59 bool "Renesas R-Car PCIe controller"
64 Say Y here if you want PCIe controller support on R-Car SoCs.
68 bool "Renesas R-Car PCIe host controller"
73 Say Y here if you want PCIe controller support on R-Car SoCs in host
77 bool "Renesas R-Car PCIe endpoint controller"
81 Say Y here if you want PCIe controller support on R-Car SoCs in
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| D | pcie-xilinx.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (c) 2012 - 2014 Xilinx, Inc.
7 * Based on the Tegra PCIe driver
89 /* ECAM definitions */
97 * struct xilinx_pcie_port - PCIe port information
120 return readl(port->reg_base + reg); in pcie_read()
125 writel(val, port->reg_base + reg); in pcie_write()
135 * xilinx_pcie_clear_err_interrupts - Clear Error Interrupts
140 struct device *dev = port->dev; in xilinx_pcie_clear_err_interrupts()
152 * xilinx_pcie_valid_device - Check if a valid device is present on bus
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| D | pcie-xilinx-nwl.c | 1 // SPDX-License-Identifier: GPL-2.0+
4 * Based on pcie-xilinx.c, pci-tegra.c
6 * (C) Copyright 2014 - 2015, Xilinx, Inc.
32 /* Egress - Bridge translation registers */
42 /* Ingress - address translations */
50 /* Rxed msg fifo - Interrupt status registers */
178 return readl(pcie->breg_base + off); in nwl_bridge_readl()
183 writel(val, pcie->breg_base + off); in nwl_bridge_writel()
188 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT) in nwl_pcie_link_up()
195 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT) in nwl_phy_link_up()
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| D | pci-xgene.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * APM X-Gene PCIe Driver
20 #include <linux/pci-acpi.h>
21 #include <linux/pci-ecam.h>
77 return readl(port->csr_base + reg); in xgene_pcie_readl()
82 writel(val, port->csr_base + reg); in xgene_pcie_writel()
95 return (struct xgene_pcie_port *)(bus->sysdata); in pcie_bus_to_port()
97 cfg = bus->sysdata; in pcie_bus_to_port()
98 return (struct xgene_pcie_port *)(cfg->priv); in pcie_bus_to_port()
109 if (bus->number >= (bus->primary + 1)) in xgene_pcie_get_cfg_base()
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| D | pci-tegra.c | 1 // SPDX-License-Identifier: GPL-2.0+
8 * Based on NVIDIA PCIe driver
9 * Copyright (c) 2008-2009, NVIDIA Corporation.
11 * Bits taken from arch/arm/mach-dove/pcie.c
270 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
397 writel(value, pcie->afi + offset); in afi_writel()
402 return readl(pcie->afi + offset); in afi_readl()
408 writel(value, pcie->pads + offset); in pads_writel()
413 return readl(pcie->pads + offset); in pads_readl()
417 * The configuration space mapping on Tegra is somewhat similar to the ECAM
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| /kernel/linux/linux-4.19/drivers/pci/controller/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
75 bool "Renesas R-Car Gen2 Internal PCI controller"
79 Say Y here if you want internal PCI support on R-Car Gen2 SoC.
81 built-in EHCI/OHCI host controller present on each one.
84 bool "Renesas R-Car PCIe controller"
88 Say Y here if you want PCIe controller support on R-Car SoCs.
111 bool "X-Gene PCIe controller"
115 Say Y here if you want internal PCI support on APM X-Gene SoC.
120 bool "X-Gene v1 PCIe MSI feature"
125 Say Y here if you want PCIe MSI support for the APM X-Gene v1 SoC.
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| D | pcie-xilinx.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (c) 2012 - 2014 Xilinx, Inc.
7 * Based on the Tegra PCIe driver
89 /* ECAM definitions */
97 * struct xilinx_pcie_port - PCIe port information
122 return readl(port->reg_base + reg); in pcie_read()
127 writel(val, port->reg_base + reg); in pcie_write()
137 * xilinx_pcie_clear_err_interrupts - Clear Error Interrupts
142 struct device *dev = port->dev; in xilinx_pcie_clear_err_interrupts()
154 * xilinx_pcie_valid_device - Check if a valid device is present on bus
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| D | pcie-xilinx-nwl.c | 1 // SPDX-License-Identifier: GPL-2.0+
4 * Based on pcie-xilinx.c, pci-tegra.c
6 * (C) Copyright 2014 - 2015, Xilinx, Inc.
31 /* Egress - Bridge translation registers */
41 /* Ingress - address translations */
49 /* Rxed msg fifo - Interrupt status registers */
177 return readl(pcie->breg_base + off); in nwl_bridge_readl()
182 writel(val, pcie->breg_base + off); in nwl_bridge_writel()
187 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT) in nwl_pcie_link_up()
194 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT) in nwl_phy_link_up()
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| D | pci-xgene.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * APM X-Gene PCIe Driver
20 #include <linux/pci-acpi.h>
21 #include <linux/pci-ecam.h>
77 return readl(port->csr_base + reg); in xgene_pcie_readl()
82 writel(val, port->csr_base + reg); in xgene_pcie_writel()
95 return (struct xgene_pcie_port *)(bus->sysdata); in pcie_bus_to_port()
97 cfg = bus->sysdata; in pcie_bus_to_port()
98 return (struct xgene_pcie_port *)(cfg->priv); in pcie_bus_to_port()
109 if (bus->number >= (bus->primary + 1)) in xgene_pcie_get_cfg_base()
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| D | pci-tegra.c | 1 // SPDX-License-Identifier: GPL-2.0+
8 * Based on NVIDIA PCIe driver
9 * Copyright (c) 2008-2009, NVIDIA Corporation.
11 * Bits taken from arch/arm/mach-dove/pcie.c
219 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
334 writel(value, pcie->afi + offset); in afi_writel()
339 return readl(pcie->afi + offset); in afi_readl()
345 writel(value, pcie->pads + offset); in pads_writel()
350 return readl(pcie->pads + offset); in pads_readl()
354 * The configuration space mapping on Tegra is somewhat similar to the ECAM
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| /kernel/linux/linux-5.10/arch/x86/pci/ |
| D | common.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Low-Level PCI Support for PC
5 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
10 #include <linux/pci-acpi.h>
35 int pcibios_last_bus = -1;
44 return raw_pci_ops->read(domain, bus, devfn, reg, len, val); in raw_pci_read()
46 return raw_pci_ext_ops->read(domain, bus, devfn, reg, len, val); in raw_pci_read()
47 return -EINVAL; in raw_pci_read()
54 return raw_pci_ops->write(domain, bus, devfn, reg, len, val); in raw_pci_write()
56 return raw_pci_ext_ops->write(domain, bus, devfn, reg, len, val); in raw_pci_write()
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| /kernel/linux/linux-4.19/arch/x86/pci/ |
| D | common.c | 2 * Low-Level PCI Support for PC
4 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
9 #include <linux/pci-acpi.h>
33 int pcibios_last_bus = -1;
42 return raw_pci_ops->read(domain, bus, devfn, reg, len, val); in raw_pci_read()
44 return raw_pci_ext_ops->read(domain, bus, devfn, reg, len, val); in raw_pci_read()
45 return -EINVAL; in raw_pci_read()
52 return raw_pci_ops->write(domain, bus, devfn, reg, len, val); in raw_pci_write()
54 return raw_pci_ext_ops->write(domain, bus, devfn, reg, len, val); in raw_pci_write()
55 return -EINVAL; in raw_pci_write()
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/hisilicon/ |
| D | hip06.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip06-d03";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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| D | hip07.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip07-d05";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
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| /kernel/linux/linux-4.19/arch/arm64/boot/dts/hisilicon/ |
| D | hip06.dtsi | 12 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 compatible = "hisilicon,hip06-d03";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 compatible = "arm,psci-0.2";
26 #address-cells = <1>;
27 #size-cells = <0>;
29 cpu-map {
90 compatible = "arm,cortex-a57", "arm,armv8";
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| D | hip07.dtsi | 12 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 compatible = "hisilicon,hip07-d05";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 compatible = "arm,psci-0.2";
26 #address-cells = <1>;
27 #size-cells = <0>;
29 cpu-map {
273 compatible = "arm,cortex-a72", "arm,armv8";
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| /kernel/linux/linux-5.10/drivers/net/ethernet/realtek/ |
| D | r8169_main.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
26 #include <linux/dma-mapping.h>
38 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
39 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
40 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
41 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
42 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
43 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
44 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
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| /kernel/linux/linux-4.19/drivers/net/ethernet/realtek/ |
| D | r8169.c | 5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
27 #include <linux/dma-mapping.h>
31 #include <linux/pci-aspm.h>
37 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
38 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
39 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
40 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
41 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
42 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
43 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
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