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/kernel/linux/linux-4.19/arch/arm64/boot/dts/exynos/
Dexynos5433-tmu.dtsi136 g3d_thermal: g3d-thermal {
141 g3d_alert_0: g3d-alert-0 {
146 g3d_alert_1: g3d-alert-1 {
151 g3d_alert_2: g3d-alert-2 {
156 g3d_alert_3: g3d-alert-3 {
161 g3d_alert_4: g3d-alert-4 {
166 g3d_alert_5: g3d-alert-5 {
171 g3d_alert_6: g3d-alert-6 {
/kernel/linux/linux-5.10/arch/arm64/boot/dts/exynos/
Dexynos5433-tmu.dtsi143 g3d_thermal: g3d-thermal {
148 g3d_alert_0: g3d-alert-0 {
153 g3d_alert_1: g3d-alert-1 {
158 g3d_alert_2: g3d-alert-2 {
163 g3d_alert_3: g3d-alert-3 {
168 g3d_alert_4: g3d-alert-4 {
173 g3d_alert_5: g3d-alert-5 {
178 g3d_alert_6: g3d-alert-6 {
/kernel/linux/linux-4.19/drivers/cpufreq/
Ds5pv210-cpufreq.c175 * ONEDRAM, MFC, G3D }
296 * 1. Temporary Change divider for MFC and G3D in s5pv210_target()
305 /* For MFC, G3D dividing */ in s5pv210_target()
311 * 2. Change SCLKA2M(200Mhz)to SCLKMPLL in MFC_MUX, G3D MUX in s5pv210_target()
397 * to SCLKA2M(200Mhz) in MFC_MUX and G3D MUX in s5pv210_target()
411 * 8. Change divider for MFC and G3D in s5pv210_target()
420 /* For MFC, G3D dividing */ in s5pv210_target()
/kernel/linux/linux-5.10/drivers/cpufreq/
Ds5pv210-cpufreq.c172 * ONEDRAM, MFC, G3D }
293 * 1. Temporary Change divider for MFC and G3D in s5pv210_target()
302 /* For MFC, G3D dividing */ in s5pv210_target()
308 * 2. Change SCLKA2M(200Mhz)to SCLKMPLL in MFC_MUX, G3D MUX in s5pv210_target()
394 * to SCLKA2M(200Mhz) in MFC_MUX and G3D MUX in s5pv210_target()
408 * 8. Change divider for MFC and G3D in s5pv210_target()
417 /* For MFC, G3D dividing */ in s5pv210_target()
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/devfreq/
Dexynos-bus.txt61 |--- G3D
75 |--- G3D
93 |--- G3D
111 |--- G3D
150 |--- G3D
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/devfreq/
Dexynos-bus.txt63 |--- G3D
77 |--- G3D
95 |--- G3D
113 |--- G3D
152 |--- G3D
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dexynos5260-clock.txt59 8) "samsung,exynos5260-clock-g3d"
119 Input clocks for g3d clock controller:
Dexynos5433-clock.txt10 which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS
31 - "samsung,exynos5433-cmu-g3d" - clock controller compatible for CMU_G3D
123 Input clocks for g3d clock controller:
353 compatible = "samsung,exynos5433-cmu-g3d";
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/clock/
Dexynos5260-clock.txt59 8) "samsung,exynos5260-clock-g3d"
119 Input clocks for g3d clock controller:
Dexynos5433-clock.txt10 which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS
31 - "samsung,exynos5433-cmu-g3d" - clock controller compatible for CMU_G3D
121 Input clocks for g3d clock controller:
345 compatible = "samsung,exynos5433-cmu-g3d";
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/hisilicon/controller/
Dhi6220-domain-ctrl.yaml15 controller(e.g. codec, G3D ...) and the Power Management domain
/kernel/linux/linux-4.19/drivers/clk/mediatek/
DMakefile12 obj-$(CONFIG_COMMON_CLK_MT2701_G3DSYS) += clk-mt2701-g3d.o
Dclk-mt2701-g3d.c90 .name = "clk-mt2701-g3d",
/kernel/linux/linux-5.10/drivers/clk/mediatek/
Dclk-mt2701-g3d.c90 .name = "clk-mt2701-g3d",
DMakefile29 obj-$(CONFIG_COMMON_CLK_MT2701_G3DSYS) += clk-mt2701-g3d.o
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/devfreq/event/
Dexynos-ppmu.txt8 usages of each IP (DMC, CPU, RIGHTBUS, LEFTBUS, CAM interface, LCD, G3D, MFC).
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/devfreq/event/
Dexynos-ppmu.txt8 usages of each IP (DMC, CPU, RIGHTBUS, LEFTBUS, CAM interface, LCD, G3D, MFC).
/kernel/linux/linux-5.10/drivers/clk/hisilicon/
Dclk-hi3660-stub.c107 DEFINE_CLK_STUB(HI3660_CLK_STUB_GPU, 0x0003030A, "clk-g3d")
/kernel/linux/linux-4.19/drivers/clk/hisilicon/
Dclk-hi3660-stub.c116 DEFINE_CLK_STUB(HI3660_CLK_STUB_GPU, 0x0003030A, "clk-g3d")
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dexynos5260.dtsi125 compatible = "samsung,exynos5260-clock-g3d";
/kernel/linux/linux-5.10/drivers/clk/samsung/
Dclk-exynos5420.c1265 GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9,
1270 { GATE_IP_G3D, 0x3ff, 0x3ff }, /* G3D gates */
1351 .pd_name = "G3D",
1656 * Keep top part of G3D clock path enabled permanently to ensure in exynos5x_clk_init()
1658 * main G3D clock enablement status. in exynos5x_clk_init()
Dclk-s5pv210.c630 GATE(CLK_G3D, "g3d", "dout_hclkm", CLK_GATE_IP0, 8, 0, 0),
692 GATE(CLK_G3D, "g3d", "dout_hclkd", CLK_GATE_IP0, 8, 0, 0),
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/hisilicon/
Dhisilicon.txt151 domain(e.g. codec, G3D ...) for mobile platform.
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dexynos5260.dtsi129 compatible = "samsung,exynos5260-clock-g3d";
/kernel/linux/linux-4.19/drivers/clk/samsung/
Dclk-s5pv210.c671 GATE(CLK_G3D, "g3d", "dout_hclkm", CLK_GATE_IP0, 8, 0, 0),
733 GATE(CLK_G3D, "g3d", "dout_hclkd", CLK_GATE_IP0, 8, 0, 0),

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