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/kernel/linux/linux-4.19/Documentation/devicetree/bindings/gpio/
Drenesas,gpio-rcar.txt1 * Renesas R-Car GPIO Controller
5 - compatible: should contain one or more of the following:
6 - "renesas,gpio-r8a7743": for R8A7743 (RZ/G1M) compatible GPIO controller.
7 - "renesas,gpio-r8a7745": for R8A7745 (RZ/G1E) compatible GPIO controller.
8 - "renesas,gpio-r8a77470": for R8A77470 (RZ/G1C) compatible GPIO controller.
9 - "renesas,gpio-r8a7778": for R8A7778 (R-Car M1) compatible GPIO controller.
10 - "renesas,gpio-r8a7779": for R8A7779 (R-Car H1) compatible GPIO controller.
11 - "renesas,gpio-r8a7790": for R8A7790 (R-Car H2) compatible GPIO controller.
12 - "renesas,gpio-r8a7791": for R8A7791 (R-Car M2-W) compatible GPIO controller.
13 - "renesas,gpio-r8a7792": for R8A7792 (R-Car V2H) compatible GPIO controller.
[all …]
Dgpio.txt1 Specifying GPIO information for devices
5 -----------------
8 properties, each containing a 'gpio-list':
10 gpio-list ::= <single-gpio> [gpio-list]
11 single-gpio ::= <gpio-phandle> <gpio-specifier>
12 gpio-phandle : phandle to gpio controller node
13 gpio-specifier : Array of #gpio-cells specifying specific gpio
14 (controller specific)
16 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
17 of this GPIO for the device. While a non-existent <name> is considered valid
[all …]
Dgpio-mxs.txt1 * Freescale MXS GPIO controller
3 The Freescale MXS GPIO controller is part of MXS PIN controller. The
6 As the GPIO controller is embedded in the PIN controller and all the
7 GPIO ports share the same IO space with PIN controller, the GPIO node
8 will be represented as sub-nodes of MXS pinctrl node.
10 Required properties for GPIO node:
11 - compatible : Should be "fsl,<soc>-gpio". The supported SoCs include
13 - interrupts : Should be the port interrupt shared by all 32 pins.
14 - gpio-controller : Marks the device node as a gpio controller.
15 - #gpio-cells : Should be two. The first cell is the pin number and
[all …]
D8xxx_gpio.txt1 GPIO controllers on MPC8xxx SoCs
3 This is for the non-QE/CPM/GUTs GPIO controllers as found on
6 Every GPIO controller node must have #gpio-cells property defined,
7 this information will be used to translate gpio-specifiers.
8 See bindings/gpio/gpio.txt for details of how to specify GPIO
11 The GPIO module usually is connected to the SoC's internal interrupt
12 controller, see bindings/interrupt-controller/interrupts.txt (the
13 interrupt client nodes section) for details how to specify this GPIO
16 The GPIO module may serve as another interrupt controller (cascaded to
17 the SoC's internal interrupt controller). See the interrupt controller
[all …]
Dnvidia,tegra186-gpio.txt1 NVIDIA Tegra186 GPIO controllers
3 Tegra186 contains two GPIO controllers; a main controller and an "AON"
4 controller. This binding document applies to both controllers. The register
9 The Tegra186 GPIO controller allows software to set the IO direction of, and
10 read/write the value of, numerous GPIO signals. Routing of GPIO signals to
11 package balls is under the control of a separate pin controller HW block. Two
14 a) Security registers, which allow configuration of allowed access to the GPIO
17 varies between the different GPIO controllers.
20 that wishes to configure access to the GPIO registers needs access to these
21 registers to do so. Code which simply wishes to read or write GPIO data does not
[all …]
Dbrcm,brcmstb-gpio.txt1 Broadcom STB "UPG GIO" GPIO controller
3 The controller's registers are organized as sets of eight 32-bit
5 interrupt is shared for all of the banks handled by the controller.
9 - compatible:
10 Must be "brcm,brcmstb-gpio"
12 - reg:
14 the brcmstb GPIO controller registers
16 - #gpio-cells:
17 Should be <2>. The first cell is the pin number (within the controller's
19 bit[0]: polarity (0 for active-high, 1 for active-low)
[all …]
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dexynos5410-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Exynos5410 SoC pin-mux and pin-config device tree source
9 #include <dt-bindings/pinctrl/samsung.h>
13 gpio-controller;
14 #gpio-cells = <2>;
16 interrupt-controller;
17 #interrupt-cells = <2>;
21 gpio-controller;
22 #gpio-cells = <2>;
24 interrupt-controller;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dexynos5410-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Exynos5410 SoC pin-mux and pin-config device tree source
9 #include <dt-bindings/pinctrl/samsung.h>
13 gpio-controller;
14 #gpio-cells = <2>;
16 interrupt-controller;
17 #interrupt-cells = <2>;
21 gpio-controller;
22 #gpio-cells = <2>;
24 interrupt-controller;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/gpio/
Dgpio.txt1 Specifying GPIO information for devices
5 -----------------
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
14 GPIO properties can contain one or more GPIO phandles, but only in exceptional
23 The following example could be used to describe GPIO pins used as device enable
24 and bit-banged data signals:
27 gpio-controller;
28 #gpio-cells = <2>;
[all …]
D8xxx_gpio.txt1 GPIO controllers on MPC8xxx SoCs
3 This is for the non-QE/CPM/GUTs GPIO controllers as found on
6 Every GPIO controller node must have #gpio-cells property defined,
7 this information will be used to translate gpio-specifiers.
8 See bindings/gpio/gpio.txt for details of how to specify GPIO
11 The GPIO module usually is connected to the SoC's internal interrupt
12 controller, see bindings/interrupt-controller/interrupts.txt (the
13 interrupt client nodes section) for details how to specify this GPIO
16 The GPIO module may serve as another interrupt controller (cascaded to
17 the SoC's internal interrupt controller). See the interrupt controller
[all …]
Dgpio-mxs.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-mxs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale MXS GPIO controller
10 - Shawn Guo <shawnguo@kernel.org>
11 - Anson Huang <Anson.Huang@nxp.com>
14 The Freescale MXS GPIO controller is part of MXS PIN controller.
16 As the GPIO controller is embedded in the PIN controller and all the
17 GPIO ports share the same IO space with PIN controller, the GPIO node
[all …]
Dnvidia,tegra186-gpio.txt1 NVIDIA Tegra186 GPIO controllers
3 Tegra186 contains two GPIO controllers; a main controller and an "AON"
4 controller. This binding document applies to both controllers. The register
9 The Tegra186 GPIO controller allows software to set the IO direction of, and
10 read/write the value of, numerous GPIO signals. Routing of GPIO signals to
11 package balls is under the control of a separate pin controller HW block. Two
14 a) Security registers, which allow configuration of allowed access to the GPIO
17 varies between the different GPIO controllers.
20 that wishes to configure access to the GPIO registers needs access to these
21 registers to do so. Code which simply wishes to read or write GPIO data does not
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/exynos/
Dexynos7-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos7 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as
12 #include <dt-bindings/pinctrl/samsung.h>
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 interrupt-parent = <&gic>;
21 #interrupt-cells = <2>;
33 gpio-controller;
[all …]
Dexynos5433-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device
12 #include <dt-bindings/pinctrl/samsung.h>
17 samsung,pin-function = <EXYNOS_PIN_FUNC_ ##_func>; \
18 samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \
19 samsung,pin-drv = <EXYNOS5433_PIN_DRV_ ##_drv>; \
24 gpio-controller;
25 #gpio-cells = <2>;
27 interrupt-controller;
[all …]
/kernel/linux/linux-4.19/arch/arm64/boot/dts/exynos/
Dexynos7-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos7 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos7 SoC pin-mux and pin-config options are listed as
12 #include <dt-bindings/pinctrl/samsung.h>
16 gpio-controller;
17 #gpio-cells = <2>;
19 interrupt-controller;
20 interrupt-parent = <&gic>;
21 #interrupt-cells = <2>;
33 gpio-controller;
[all …]
Dexynos5433-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source
8 * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device
12 #include <dt-bindings/pinctrl/samsung.h>
17 samsung,pin-function = <EXYNOS_PIN_FUNC_ ##_func>; \
18 samsung,pin-pud = <EXYNOS_PIN_PULL_ ##_pull>; \
19 samsung,pin-drv = <EXYNOS5433_PIN_DRV_ ##_drv>; \
24 gpio-controller;
25 #gpio-cells = <2>;
27 interrupt-controller;
[all …]
/kernel/linux/linux-5.10/arch/powerpc/boot/dts/
Dmucmc52.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Copyright 2006-2007 Secret Lab Technologies Ltd.
12 /* Timer pins that need to be in GPIO mode */
13 &gpt0 { gpio-controller; };
14 &gpt1 { gpio-controller; };
15 &gpt2 { gpio-controller; };
16 &gpt3 { gpio-controller; };
50 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
54 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
70 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/
Dbrcm,iproc-gpio.txt1 Broadcom iProc GPIO/PINCONF Controller
5 - compatible:
6 "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that
7 supports full-featured pinctrl and GPIO functions used in various iProc
10 May contain an SoC-specific compatibility string to accommodate any
11 SoC-specific features
13 "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or
14 "brcm,cygnus-crmu-gpio" for Cygnus SoCs
16 "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support
19 "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/pinctrl/
Dbrcm,iproc-gpio.txt1 Broadcom iProc GPIO/PINCONF Controller
5 - compatible:
6 "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that
7 supports full-featured pinctrl and GPIO functions used in various iProc
10 May contain an SoC-specific compatibility string to accommodate any
11 SoC-specific features
13 "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or
14 "brcm,cygnus-crmu-gpio" for Cygnus SoCs
16 "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support
19 "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general
[all …]
/kernel/linux/linux-4.19/arch/powerpc/boot/dts/
Dmucmc52.dts6 * Copyright 2006-2007 Secret Lab Technologies Ltd.
16 /* Timer pins that need to be in GPIO mode */
17 &gpt0 { gpio-controller; };
18 &gpt1 { gpio-controller; };
19 &gpt2 { gpio-controller; };
20 &gpt3 { gpio-controller; };
54 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
58 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
74 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
78 phy-handle = <&phy0>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/hisilicon/
Dhi3670.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/hi3670-clock.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "arm,psci-0.2";
24 #address-cells = <2>;
25 #size-cells = <0>;
27 cpu-map {
[all …]
/kernel/linux/linux-5.10/arch/arc/boot/dts/
Dabilis_tb101.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
15 bus-frequency = <166666666>;
18 clock-frequency = <1000000000>;
21 clock-mult = <1>;
22 clock-div = <2>;
25 clock-mult = <1>;
26 clock-div = <6>;
31 pctl_tsin_s0: pctl-tsin-s0 { /* Serial TS-in 0 */
34 pctl_tsin_s1: pctl-tsin-s1 { /* Serial TS-in 1 */
37 pctl_gpio_a: pctl-gpio-a { /* GPIO bank A */
[all …]
Dabilis_tb100.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
15 bus-frequency = <166666666>;
18 clock-frequency = <1000000000>;
21 clock-mult = <1>;
22 clock-div = <2>;
25 clock-mult = <1>;
26 clock-div = <6>;
31 pctl_tsin_s0: pctl-tsin-s0 { /* Serial TS-in 0 */
34 pctl_tsin_s1: pctl-tsin-s1 { /* Serial TS-in 1 */
37 pctl_gpio_a: pctl-gpio-a { /* GPIO bank A */
[all …]
/kernel/linux/linux-4.19/arch/arc/boot/dts/
Dabilis_tb101.dtsi19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 bus-frequency = <166666666>;
30 clock-frequency = <1000000000>;
33 clock-mult = <1>;
34 clock-div = <2>;
37 clock-mult = <1>;
38 clock-div = <6>;
43 pctl_tsin_s0: pctl-tsin-s0 { /* Serial TS-in 0 */
46 pctl_tsin_s1: pctl-tsin-s1 { /* Serial TS-in 1 */
49 pctl_gpio_a: pctl-gpio-a { /* GPIO bank A */
[all …]
Dabilis_tb100.dtsi19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 bus-frequency = <166666666>;
30 clock-frequency = <1000000000>;
33 clock-mult = <1>;
34 clock-div = <2>;
37 clock-mult = <1>;
38 clock-div = <6>;
43 pctl_tsin_s0: pctl-tsin-s0 { /* Serial TS-in 0 */
46 pctl_tsin_s1: pctl-tsin-s1 { /* Serial TS-in 1 */
49 pctl_gpio_a: pctl-gpio-a { /* GPIO bank A */
[all …]

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