Searched full:harts (Results 1 – 18 of 18) sorted by relevance
| /kernel/linux/linux-5.10/arch/riscv/kernel/ |
| D | sbi.c | 97 * sbi_shutdown() - Remove all the harts from executing supervisor code.
363 * @hart_mask: A cpu mask containing all the target harts.
374 * sbi_remote_fence_i() - Execute FENCE.I instruction on given remote harts.
375 * @hart_mask: A cpu mask containing all the target harts.
388 * harts for the specified virtual address range.
389 * @hart_mask: A cpu mask containing all the target harts.
406 * remote harts for a virtual address range belonging to a specific ASID.
408 * @hart_mask: A cpu mask containing all the target harts.
427 * harts for the specified guest physical address range.
428 * @hart_mask: A cpu mask containing all the target harts.
[all …]
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| D | head.S | 180 /* We lack SMP support or have too many harts, so park this hart */
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| /kernel/linux/linux-5.10/arch/riscv/mm/ |
| D | cacheflush.c | 31 * informs the remote harts they need to flush their local instruction caches.
34 * IPIs for harts that are not currently executing a MM context and instead
54 * Flush the I$ of other harts concurrently executing, and mark them as in flush_icache_mm()
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| D | context.c | 15 * shoot downs, so instead we send an IPI that informs the remote harts they
18 * machine, ie 'make -j') we avoid the IPIs for harts that are not currently
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| /kernel/linux/linux-4.19/arch/riscv/kernel/ |
| D | smpboot.c | 75 * On RISC-V systems, all harts boot on their own accord. Our _start in __cpu_up()
77 * of the harts to spin in a loop waiting for their stack pointer to be in __cpu_up()
79 * the spinning harts that they can continue the boot process. in __cpu_up()
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| D | smp.c | 120 * informs the remote harts they need to flush their local instruction caches.
123 * IPIs for harts that are not currently executing a MM context and instead
143 * Flush the I$ of other harts concurrently executing, and mark them as in flush_icache_mm()
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| D | head.S | 149 /* We lack SMP support or have too many harts, so park this hart */
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| /kernel/linux/linux-4.19/arch/riscv/include/asm/ |
| D | mmu_context.h | 45 * shoot downs, so instead we send an IPI that informs the remote harts they
48 * machine, ie 'make -j') we avoid the IPIs for harts that are not currently
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/riscv/ |
| D | cpus.txt | 27 threads. Therefore this system has four harts.
89 This system contains two harts: a hart marked as disabled that's used for
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/ |
| D | sifive,clint.yaml | 17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
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| /kernel/linux/linux-5.10/arch/csky/abiv2/ |
| D | cacheflush.c | 74 * Flush the I$ of other harts concurrently executing, and mark them as in flush_icache_mm_range()
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/interrupt-controller/ |
| D | riscv,cpu-intc.txt | 23 a PLIC interrupt property will typically list the HLICs for all present HARTs
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| D | sifive,plic-1.0.0.txt | 10 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | riscv,cpu-intc.txt | 23 a PLIC interrupt property will typically list the HLICs for all present HARTs
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| D | sifive,plic-1.0.0.yaml | 17 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
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| /kernel/linux/linux-4.19/drivers/clocksource/ |
| D | riscv_timer.c | 42 * It is guaranteed that all the timers across all the harts are synchronized
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/riscv/ |
| D | cpus.yaml | 23 having four harts.
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| /kernel/linux/linux-5.10/drivers/clocksource/ |
| D | timer-riscv.c | 41 * It is guaranteed that all the timers across all the harts are synchronized
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