| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/display/msm/ |
| D | hdmi.txt | 1 Qualcomm adreno/snapdragon hdmi output
4 - compatible: one of the following
5 * "qcom,hdmi-tx-8996"
6 * "qcom,hdmi-tx-8994"
7 * "qcom,hdmi-tx-8084"
8 * "qcom,hdmi-tx-8974"
9 * "qcom,hdmi-tx-8660"
10 * "qcom,hdmi-tx-8960"
11 - reg: Physical base address and length of the controller's registers
12 - reg-names: "core_physical"
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/msm/ |
| D | hdmi.txt | 1 Qualcomm adreno/snapdragon hdmi output
4 - compatible: one of the following
5 * "qcom,hdmi-tx-8996"
6 * "qcom,hdmi-tx-8994"
7 * "qcom,hdmi-tx-8084"
8 * "qcom,hdmi-tx-8974"
9 * "qcom,hdmi-tx-8660"
10 * "qcom,hdmi-tx-8960"
11 - reg: Physical base address and length of the controller's registers
12 - reg-names: "core_physical"
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/bridge/ |
| D | renesas,dw-hdmi.txt | 1 Renesas Gen3 DWC HDMI TX Encoder
4 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
7 These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
9 following device-specific properties.
14 - compatible : Shall contain one or more of
15 - "renesas,r8a774a1-hdmi" for R8A774A1 (RZ/G2M) compatible HDMI TX
16 - "renesas,r8a774b1-hdmi" for R8A774B1 (RZ/G2N) compatible HDMI TX
17 - "renesas,r8a774e1-hdmi" for R8A774E1 (RZ/G2H) compatible HDMI TX
18 - "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX
19 - "renesas,r8a7796-hdmi" for R8A7796 (R-Car M3-W) compatible HDMI TX
[all …]
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| D | dw_hdmi.txt | 1 Synopsys DesignWare HDMI TX Encoder
4 This document defines device tree properties for the Synopsys DesignWare HDMI
5 TX Encoder (DWC HDMI TX). It doesn't constitue a device tree binding
6 specification by itself but is meant to be referenced by platform-specific
13 - reg: Memory mapped base address and length of the DWC HDMI TX registers.
15 - reg-io-width: Width of the registers specified by the reg property. The
19 - interrupts: Reference to the DWC HDMI TX interrupt.
21 - clocks: References to all the clocks specified in the clock-names property
22 as specified in Documentation/devicetree/bindings/clock/clock-bindings.txt.
24 - clock-names: The DWC HDMI TX uses the following clocks.
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/display/bridge/ |
| D | renesas,dw-hdmi.txt | 1 Renesas Gen3 DWC HDMI TX Encoder
4 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
7 These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
9 following device-specific properties.
14 - compatible : Shall contain one or more of
15 - "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX
16 - "renesas,r8a7796-hdmi" for R8A7796 (R-Car M3-W) compatible HDMI TX
17 - "renesas,r8a77965-hdmi" for R8A77965 (R-Car M3-N) compatible HDMI TX
18 - "renesas,rcar-gen3-hdmi" for the generic R-Car Gen3 compatible HDMI TX
20 When compatible with generic versions, nodes must list the SoC-specific
[all …]
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| D | dw_hdmi.txt | 1 Synopsys DesignWare HDMI TX Encoder
4 This document defines device tree properties for the Synopsys DesignWare HDMI
5 TX Encoder (DWC HDMI TX). It doesn't constitue a device tree binding
6 specification by itself but is meant to be referenced by platform-specific
13 - reg: Memory mapped base address and length of the DWC HDMI TX registers.
15 - reg-io-width: Width of the registers specified by the reg property. The
19 - interrupts: Reference to the DWC HDMI TX interrupt.
21 - clocks: References to all the clocks specified in the clock-names property
22 as specified in Documentation/devicetree/bindings/clock/clock-bindings.txt.
24 - clock-names: The DWC HDMI TX uses the following clocks.
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/hdmi/ |
| D | hdmi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <sound/hdmi-codec.h>
12 #include "hdmi.h"
14 void msm_hdmi_set_mode(struct hdmi *hdmi, bool power_on) in msm_hdmi_set_mode() argument
19 spin_lock_irqsave(&hdmi->reg_lock, flags); in msm_hdmi_set_mode()
22 if (!hdmi->hdmi_mode) { in msm_hdmi_set_mode()
24 hdmi_write(hdmi, REG_HDMI_CTRL, ctrl); in msm_hdmi_set_mode()
33 hdmi_write(hdmi, REG_HDMI_CTRL, ctrl); in msm_hdmi_set_mode()
34 spin_unlock_irqrestore(&hdmi->reg_lock, flags); in msm_hdmi_set_mode()
35 DBG("HDMI Core: %s, HDMI_CTRL=0x%08x", in msm_hdmi_set_mode()
[all …]
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| /kernel/linux/linux-4.19/drivers/gpu/drm/msm/hdmi/ |
| D | hdmi.c | 22 #include <sound/hdmi-codec.h>
23 #include "hdmi.h"
25 void msm_hdmi_set_mode(struct hdmi *hdmi, bool power_on) in msm_hdmi_set_mode() argument
30 spin_lock_irqsave(&hdmi->reg_lock, flags); in msm_hdmi_set_mode()
33 if (!hdmi->hdmi_mode) { in msm_hdmi_set_mode()
35 hdmi_write(hdmi, REG_HDMI_CTRL, ctrl); in msm_hdmi_set_mode()
44 hdmi_write(hdmi, REG_HDMI_CTRL, ctrl); in msm_hdmi_set_mode()
45 spin_unlock_irqrestore(&hdmi->reg_lock, flags); in msm_hdmi_set_mode()
46 DBG("HDMI Core: %s, HDMI_CTRL=0x%08x", in msm_hdmi_set_mode()
52 struct hdmi *hdmi = dev_id; in msm_hdmi_irq() local
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/ |
| D | allwinner,sun4i-a10-hdmi.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 HDMI Controller Device Tree Bindings
10 The HDMI Encoder supports the HDMI video and audio outputs, and does
14 - Chen-Yu Tsai <wens@csie.org>
15 - Maxime Ripard <mripard@kernel.org>
20 - const: allwinner,sun4i-a10-hdmi
21 - const: allwinner,sun5i-a10s-hdmi
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| D | allwinner,sun8i-a83t-dw-hdmi.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A83t DWC HDMI TX Encoder Device Tree Bindings
10 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller
14 These DT bindings follow the Synopsys DWC HDMI TX bindings defined
16 the following device-specific properties.
19 - Chen-Yu Tsai <wens@csie.org>
20 - Maxime Ripard <mripard@kernel.org>
[all …]
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| D | amlogic,meson-dw-hdmi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/display/amlogic,meson-dw-hdmi.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Amlogic specific extensions to the Synopsys Designware HDMI Controller
11 - Neil Armstrong <narmstrong@baylibre.com>
15 - A Synopsys DesignWare HDMI Controller IP
16 - A TOP control block controlling the Clocks and PHY
17 - A custom HDMI PHY in order to convert video to TMDS signal
19 | HDMI TOP |<= HPD
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/display/imx/ |
| D | hdmi.txt | 1 Freescale i.MX6 DWC HDMI TX Encoder
4 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
7 These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
9 following device-specific properties.
14 - compatible : Shall be one of "fsl,imx6q-hdmi" or "fsl,imx6dl-hdmi".
15 - reg: See dw_hdmi.txt.
16 - interrupts: HDMI interrupt number
17 - clocks: See dw_hdmi.txt.
18 - clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
19 - ports: See dw_hdmi.txt. The DWC HDMI shall have between one and four ports,
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/imx/ |
| D | hdmi.txt | 1 Freescale i.MX6 DWC HDMI TX Encoder
4 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
7 These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
9 following device-specific properties.
14 - compatible : Shall be one of "fsl,imx6q-hdmi" or "fsl,imx6dl-hdmi".
15 - reg: See dw_hdmi.txt.
16 - interrupts: HDMI interrupt number
17 - clocks: See dw_hdmi.txt.
18 - clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
19 - ports: See dw_hdmi.txt. The DWC HDMI shall have between one and four ports,
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/display/rockchip/ |
| D | dw_hdmi-rockchip.txt | 1 Rockchip DWC HDMI TX Encoder
4 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
7 These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
9 following device-specific properties.
14 - compatible: should be one of the following:
15 "rockchip,rk3288-dw-hdmi"
16 "rockchip,rk3399-dw-hdmi"
17 - reg: See dw_hdmi.txt.
18 - reg-io-width: See dw_hdmi.txt. Shall be 4.
19 - interrupts: HDMI interrupt number
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/rockchip/ |
| D | dw_hdmi-rockchip.txt | 1 Rockchip DWC HDMI TX Encoder
4 The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
7 These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
9 following device-specific properties.
14 - compatible: should be one of the following:
15 "rockchip,rk3228-dw-hdmi"
16 "rockchip,rk3288-dw-hdmi"
17 "rockchip,rk3328-dw-hdmi"
18 "rockchip,rk3399-dw-hdmi"
19 - reg: See dw_hdmi.txt.
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/display/ |
| D | amlogic,meson-vpu.txt | 7 DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
9 D |-------| |----| | | | | HDMI PLL |
10 D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
11 R |-------| |----| Processing | | | | |
12 | osd2 | | | |---| Enci ----------|----|-----VDAC------|
13 R |-------| CSC |----| Scalers | | Encp ----------|----|----HDMI-TX----|
14 A | osd1 | | | Blenders | | Encl ----------|----|---------------|
15 M |-------|______|----|____________| |________________| | |
20 ---------------------
28 --------------------------
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| D | amlogic,meson-dw-hdmi.txt | 1 Amlogic specific extensions to the Synopsys Designware HDMI Controller
5 - A Synopsys DesignWare HDMI Controller IP
6 - A TOP control block controlling the Clocks and PHY
7 - A custom HDMI PHY in order to convert video to TMDS signal
9 | HDMI TOP |<= HPD
12 | Synopsys HDMI | HDMI PHY |=> TMDS
16 The HDMI TOP block only supports HPD sensing.
17 The Synopsys HDMI Controller interrupt is routed through the
19 Communication to the TOP Block and the Synopsys HDMI Controller is done
21 The HDMI PHY is configured by registers in the HHI register block.
[all …]
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| /kernel/linux/linux-5.10/drivers/media/i2c/adv748x/ |
| D | adv748x-csi2.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for Analog Devices ADV748X CSI-2 Transmitter
11 #include <media/v4l2-ctrls.h>
12 #include <media/v4l2-device.h>
13 #include <media/v4l2-ioctl.h>
17 static int adv748x_csi2_set_virtual_channel(struct adv748x_csi2 *tx, in adv748x_csi2_set_virtual_channel() argument
20 return tx_write(tx, ADV748X_CSI_VC_REF, vc << ADV748X_CSI_VC_REF_SHIFT); in adv748x_csi2_set_virtual_channel()
26 * @tx: CSI2 private entity
29 * @src_pad: Pad number of source to link to this @tx
35 static int adv748x_csi2_register_link(struct adv748x_csi2 *tx, in adv748x_csi2_register_link() argument
[all …]
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| D | adv748x-core.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for Analog Devices ADV748X HDMI receiver with AFE
21 #include <linux/v4l2-dv-timings.h>
23 #include <media/v4l2-ctrls.h>
24 #include <media/v4l2-device.h>
25 #include <media/v4l2-dv-timings.h>
26 #include <media/v4l2-fwnode.h>
27 #include <media/v4l2-ioctl.h>
31 /* -----------------------------------------------------------------------------
48 ADV748X_REGMAP_CONF("hdmi"),
[all …]
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| /kernel/linux/linux-5.10/sound/soc/qcom/ |
| D | lpass.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2010-2011,2013-2015,2020 The Linux Foundation. All rights reserved.
5 * lpass.h - Definitions for the QTi LPASS
15 #include <dt-bindings/sound/qcom,lpass.h>
16 #include "lpass-hdmi.h"
27 return -EINVAL; \
58 /* AHB-I/X bus clocks inside the low-power audio subsystem (LPASS) */
76 /* low-power audio interface (LPAIF) registers */
80 /* regmap backed by the low-power audio interface (LPAIF) registers */
84 /* interrupts from the low-power audio interface (LPAIF) */
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/sun4i/ |
| D | sun4i_hdmi_i2c.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
25 static int fifo_transfer(struct sun4i_hdmi *hdmi, u8 *buf, int len, bool read) in fifo_transfer() argument
41 (hdmi->variant->ddc_fifo_thres_incl ? 0 : 1); in fifo_transfer()
45 * For TX the threshold is for an empty FIFO. in fifo_transfer()
50 if (regmap_field_read_poll_timeout(hdmi->field_ddc_int_status, reg, in fifo_transfer()
53 return -ETIMEDOUT; in fifo_transfer()
56 return -EIO; in fifo_transfer()
59 readsb(hdmi->base + hdmi->variant->ddc_fifo_reg, buf, len); in fifo_transfer()
61 writesb(hdmi->base + hdmi->variant->ddc_fifo_reg, buf, len); in fifo_transfer()
[all …]
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| /kernel/linux/linux-4.19/drivers/gpu/drm/sun4i/ |
| D | sun4i_hdmi_i2c.c | 2 * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
29 static int fifo_transfer(struct sun4i_hdmi *hdmi, u8 *buf, int len, bool read) in fifo_transfer() argument
45 (hdmi->variant->ddc_fifo_thres_incl ? 0 : 1); in fifo_transfer()
49 * For TX the threshold is for an empty FIFO. in fifo_transfer()
54 if (regmap_field_read_poll_timeout(hdmi->field_ddc_int_status, reg, in fifo_transfer()
57 return -ETIMEDOUT; in fifo_transfer()
60 return -EIO; in fifo_transfer()
63 readsb(hdmi->base + hdmi->variant->ddc_fifo_reg, buf, len); in fifo_transfer()
65 writesb(hdmi->base + hdmi->variant->ddc_fifo_reg, buf, len); in fifo_transfer()
68 regmap_field_force_write(hdmi->field_ddc_int_status, in fifo_transfer()
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/display/sunxi/ |
| D | sun4i-drm.txt | 13 Frontend 0 [0] ------- [0] Backend 0 [0] ------- [0] TCON 0
14 [1] -- -- [1] [1] -- -- [1]
18 [0] -- -- [0] [0] -- -- [0]
19 Frontend 1 [1] ------- [1] Backend 1 [1] ------- [1] TCON 1
25 The same rule also applies to DE 2.0 mixer-TCON connections:
27 Mixer 0 [0] ----------- [0] TCON 0
28 [1] ---- ---- [1]
32 [0] ---- ---- [0]
33 Mixer 1 [1] ----------- [1] TCON 1
35 HDMI Encoder
[all …]
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| /kernel/linux/linux-4.19/arch/arm64/boot/dts/amlogic/ |
| D | meson-gxbb-odroidc2.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include "meson-gxbb.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
14 compatible = "hardkernel,odroid-c2", "amlogic,meson-gxbb";
15 model = "Hardkernel ODROID-C2";
23 stdout-path = "serial0:115200n8";
31 usb_otg_pwr: regulator-usb-pwrs {
32 compatible = "regulator-fixed";
34 regulator-name = "USB_OTG_PWR";
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/display/mediatek/ |
| D | mediatek,hdmi.txt | 1 Mediatek HDMI Encoder
4 The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
8 - compatible: Should be "mediatek,<chip>-hdmi".
9 - reg: Physical base address and length of the controller's registers
10 - interrupts: The interrupt signal from the function block.
11 - clocks: device clocks
12 See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
13 - clock-names: must contain "pixel", "pll", "bclk", and "spdif".
14 - phys: phandle link to the HDMI PHY node.
15 See Documentation/devicetree/bindings/phy/phy-bindings.txt for details.
[all …]
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