| /kernel/linux/linux-4.19/drivers/usb/dwc3/ |
| D | Kconfig | 2 tristate "DesignWare USB3 DRD Core Support"
7 USB controller based on the DesignWare USB3 IP Core.
61 AM437x use this IP for USB2/3 functionality.
70 Recent Exynos5 SoCs ship with one DesignWare Core USB3 IP inside,
74 tristate "PCIe-based Platforms"
78 If you're using the DesignWare Core IP with a PCIe (but not HAPS
82 tristate "Synopsys PCIe-based HAPS Platforms"
86 If you're using the DesignWare Core IP with a Synopsys PCIe HAPS
103 Currently supports Xilinx and Qualcomm DWC USB3 IP.
111 STMicroelectronics SoCs with one DesignWare Core USB3 IP
[all …]
|
| /kernel/linux/linux-5.10/drivers/usb/dwc3/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
4 tristate "DesignWare USB3 DRD Core Support"
10 USB controller based on the DesignWare USB3 IP Core.
64 AM437x use this IP for USB2/3 functionality.
73 Recent Exynos5 SoCs ship with one DesignWare Core USB3 IP inside,
77 tristate "PCIe-based Platforms"
81 If you're using the DesignWare Core IP with a PCIe (but not HAPS
85 tristate "Synopsys PCIe-based HAPS Platforms"
89 If you're using the DesignWare Core IP with a Synopsys PCIe HAPS
117 Currently supports Xilinx and Qualcomm DWC USB3 IP.
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/ |
| D | xilinx.txt | 1 d) Xilinx IP cores
3 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
10 Each IP-core has a set of parameters which the FPGA designer can use to
11 control how the core is synthesized. Historically, the EDK tool would
14 device drivers how the IP cores are configured, but it requires the kernel
20 properties of the device node. In general, device nodes for IP-cores
23 (name): (generic-name)@(base-address) {
24 compatible = "xlnx,(ip-core-name)-(HW_VER)"
27 interrupt-parent = <&interrupt-controller-phandle>;
29 xlnx,(parameter1) = "(string-value)";
[all …]
|
| D | example-schema.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 # All the top-level keys are standard json-schema keywords except for
10 $id: http://devicetree.org/schemas/example-schema.yaml#
11 # $schema is the meta-schema this schema should be validated with.
12 $schema: http://devicetree.org/meta-schemas/core.yaml#
17 - Rob Herring <robh@kernel.org>
20 A more detailed multi-line description of the binding.
44 - items:
51 - enum:
[all …]
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/ |
| D | xilinx.txt | 1 d) Xilinx IP cores
3 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
10 Each IP-core has a set of parameters which the FPGA designer can use to
11 control how the core is synthesized. Historically, the EDK tool would
14 device drivers how the IP cores are configured, but it requires the kernel
20 properties of the device node. In general, device nodes for IP-cores
23 (name): (generic-name)@(base-address) {
24 compatible = "xlnx,(ip-core-name)-(HW_VER)"
27 interrupt-parent = <&interrupt-controller-phandle>;
29 xlnx,(parameter1) = "(string-value)";
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/xilinx/ |
| D | video.txt | 1 DT bindings for Xilinx video IP cores
2 -------------------------------------
4 Xilinx video IP cores process video streams by acting as video sinks and/or
8 Each video IP core is represented by an AMBA bus child node in the device
9 tree using bindings documented in this directory. Connections between the IP
10 cores are represented as defined in ../video-interfaces.txt.
16 -----------------
18 The following properties are common to all Xilinx video IP cores.
20 - xlnx,video-format: This property represents a video format transmitted on an
21 AXI bus between video IP cores, using its VF code as defined in "AXI4-Stream
[all …]
|
| D | xlnx,video.txt | 1 Xilinx Video IP Pipeline (VIPP)
2 -------------------------------
5 ---------------
7 Xilinx video IP pipeline processes video streams through one or more Xilinx
8 video IP cores. Each video IP core is represented as documented in video.txt
9 and IP core specific documentation, xlnx,v-*.txt, in this directory. The DT
11 mappings between DMAs and the video IP cores.
15 - compatible: Must be "xlnx,video".
17 - dmas, dma-names: List of one DMA specifier and identifier string (as defined
22 - ports: Video port, using the DT bindings defined in ../video-interfaces.txt.
[all …]
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/media/xilinx/ |
| D | video.txt | 1 DT bindings for Xilinx video IP cores
2 -------------------------------------
4 Xilinx video IP cores process video streams by acting as video sinks and/or
8 Each video IP core is represented by an AMBA bus child node in the device
9 tree using bindings documented in this directory. Connections between the IP
10 cores are represented as defined in ../video-interfaces.txt.
16 -----------------
18 The following properties are common to all Xilinx video IP cores.
20 - xlnx,video-format: This property represents a video format transmitted on an
21 AXI bus between video IP cores, using its VF code as defined in "AXI4-Stream
[all …]
|
| D | xlnx,video.txt | 1 Xilinx Video IP Pipeline (VIPP)
2 -------------------------------
5 ---------------
7 Xilinx video IP pipeline processes video streams through one or more Xilinx
8 video IP cores. Each video IP core is represented as documented in video.txt
9 and IP core specific documentation, xlnx,v-*.txt, in this directory. The DT
11 mappings between DMAs and the video IP cores.
15 - compatible: Must be "xlnx,video".
17 - dmas, dma-names: List of one DMA specifier and identifier string (as defined
22 - ports: Video port, using the DT bindings defined in ../video-interfaces.txt.
[all …]
|
| /kernel/linux/linux-5.10/drivers/staging/axis-fifo/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 # "Xilinx AXI-Stream FIFO IP core driver"
6 tristate "Xilinx AXI-Stream FIFO IP core driver"
9 This adds support for the Xilinx AXI-Stream FIFO IP core driver.
11 interface. The Xilinx AXI-Stream FIFO IP core can be used to interface
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/ptp/ |
| D | ptp-ines.txt | 1 ZHAW InES PTP time stamping IP core
3 The IP core needs two different kinds of nodes. The control node
7 port index within the IP core.
11 - compatible: "ines,ptp-ctrl"
12 - reg: physical address and size of the register bank
16 - timestamper: provides control node reference and
17 the port channel within the IP core
22 compatible = "ines,ptp-ctrl";
30 ethernet-phy@3 {
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/media/ |
| D | allegro.txt | 1 Device-tree bindings for the Allegro DVT video IP codecs present in the Xilinx
2 ZynqMP SoC. The IP core may either be a H.264/H.265 encoder or H.264/H.265
3 decoder ip core.
10 - compatible: value should be one of the following
11 "allegro,al5e-1.1", "allegro,al5e": encoder IP core
12 "allegro,al5d-1.1", "allegro,al5d": decoder IP core
13 - reg: base and length of the memory mapped register region and base and
15 - reg-names: must include "regs" and "sram"
16 - interrupts: shared interrupt from the MCUs to the processing system
17 - clocks: must contain an entry for each entry in clock-names
[all …]
|
| /kernel/linux/linux-5.10/Documentation/driver-api/ |
| D | xillybus.rst | 10 - Introduction
11 -- Background
12 -- Xillybus Overview
14 - Usage
15 -- User interface
16 -- Synchronization
17 -- Seekable pipes
19 - Internals
20 -- Source code organization
21 -- Pipe attributes
[all …]
|
| /kernel/linux/linux-4.19/Documentation/ |
| D | xillybus.txt | 10 - Introduction
11 -- Background
12 -- Xillybus Overview
14 - Usage
15 -- User interface
16 -- Synchronization
17 -- Seekable pipes
19 - Internals
20 -- Source code organization
21 -- Pipe attributes
[all …]
|
| /kernel/linux/linux-5.10/drivers/usb/usbip/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
4 tristate "USB/IP support"
9 This enables pushing USB packets over IP to allow remote
11 USB/IP core that is required by both drivers.
17 be called usbip-core.
25 This enables the USB/IP virtual host controller driver,
29 module will be called vhci-hcd.
32 int "Number of ports per USB/IP virtual host controller"
37 To increase number of ports available for USB/IP virtual
39 USB/IP virtual host controller.
[all …]
|
| /kernel/linux/linux-4.19/drivers/usb/usbip/ |
| D | Kconfig | 2 tristate "USB/IP support"
6 ---help---
7 This enables pushing USB packets over IP to allow remote
9 USB/IP core that is required by both drivers.
15 be called usbip-core.
22 ---help---
23 This enables the USB/IP virtual host controller driver,
27 module will be called vhci-hcd.
30 int "Number of ports per USB/IP virtual host controller"
34 ---help---
[all …]
|
| /kernel/linux/linux-4.19/drivers/staging/axis-fifo/ |
| D | Kconfig | 2 # "Xilinx AXI-Stream FIFO IP core driver"
5 tristate "Xilinx AXI-Stream FIFO IP core driver"
9 This adds support for the Xilinx AXI-Stream
10 FIFO IP core driver.
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/ |
| D | marvell,xenon-sdhci.txt | 2 This file documents differences between the core mmc properties
5 Multiple SDHCs might be put into a single Xenon IP, to save size and cost.
11 - compatible: should be one of the following
12 - "marvell,armada-3700-sdhci": For controllers on Armada-3700 SoC.
13 Must provide a second register area and marvell,pad-type.
14 - "marvell,armada-ap806-sdhci": For controllers on Armada AP806.
15 - "marvell,armada-cp110-sdhci": For controllers on Armada CP110.
17 - clocks:
19 Require at least input clock for Xenon IP core. For Armada AP806 and
22 - clock-names:
[all …]
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/mmc/ |
| D | marvell,xenon-sdhci.txt | 2 This file documents differences between the core mmc properties
5 Multiple SDHCs might be put into a single Xenon IP, to save size and cost.
11 - compatible: should be one of the following
12 - "marvell,armada-3700-sdhci": For controllers on Armada-3700 SoC.
13 Must provide a second register area and marvell,pad-type.
14 - "marvell,armada-ap806-sdhci": For controllers on Armada AP806.
15 - "marvell,armada-cp110-sdhci": For controllers on Armada CP110.
17 - clocks:
19 Require at least input clock for Xenon IP core. For Armada AP806 and
22 - clock-names:
[all …]
|
| /kernel/linux/linux-4.19/Documentation/networking/caif/ |
| D | Linux-CAIF.txt | 3 copyright (C) ST-Ericsson AB 2010
9 ------------
10 CAIF is a MUX protocol used by ST-Ericsson cellular modems for
15 ST-Ericsson modems support a number of transports between modem
20 ------------
22 * CAIF Socket Layer and GPRS IP Interface.
23 * CAIF Core Protocol Implementation
29 ! +------+ +------+
30 ! +------+! +------+!
31 ! ! IP !! !Socket!!
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|
| /kernel/linux/linux-5.10/Documentation/networking/caif/ |
| D | linux_caif.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 Copyright |copy| ST-Ericsson AB 2010
17 CAIF is a MUX protocol used by ST-Ericsson cellular modems for
22 ST-Ericsson modems support a number of transports between modem
31 * CAIF Socket Layer and GPRS IP Interface.
32 * CAIF Core Protocol Implementation
39 ! +------+ +------+
40 ! +------+! +------+!
41 ! ! IP !! !Socket!!
42 +-------> !interf!+ ! API !+ <- CAIF Client APIs
[all …]
|
| /kernel/linux/linux-5.10/drivers/pci/controller/dwc/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 menu "DesignWare PCI Core Support"
34 host-specific features PCI_DRA7XX_HOST must be selected and in order
35 to enable device-specific features PCI_DRA7XX_EP must be selected.
36 This uses the DesignWare core.
49 host-specific features PCI_DRA7XX_HOST must be selected and in order
50 to enable device-specific features PCI_DRA7XX_EP must be selected.
51 This uses the DesignWare core.
57 bool "Platform bus based DesignWare PCIe Controller - Host mode"
62 Enables support for the PCIe controller in the Designware IP to
[all …]
|
| /kernel/linux/linux-4.19/drivers/pci/controller/dwc/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 menu "DesignWare PCI Core Support"
34 host-specific features PCI_DRA7XX_HOST must be selected and in order
35 to enable device-specific features PCI_DRA7XX_EP must be selected.
36 This uses the DesignWare core.
49 host-specific features PCI_DRA7XX_HOST must be selected and in order
50 to enable device-specific features PCI_DRA7XX_EP must be selected.
51 This uses the DesignWare core.
57 bool "Platform bus based DesignWare PCIe Controller - Host mode"
62 Enables support for the PCIe controller in the Designware IP to
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/iio/adc/ |
| D | adi,axi-adc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/adi,axi-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AXI ADC IP core
10 - Michael Hennerich <michael.hennerich@analog.com>
11 - Alexandru Ardelean <alexandru.ardelean@analog.com>
14 Analog Devices Generic AXI ADC IP core for interfacing an ADC device
18 interface for the actual ADC, while this IP core will interface
19 to the data-lines of the ADC and handle the streaming of data into
[all …]
|
| /kernel/linux/linux-4.19/fs/xfs/ |
| D | xfs_trans_inode.c | 1 // SPDX-License-Identifier: GPL-2.0
25 * If lock_flags is non-zero the inode will be unlocked on transaction commit.
30 struct xfs_inode *ip, in xfs_trans_ijoin() argument
35 ASSERT(xfs_isilocked(ip, XFS_ILOCK_EXCL)); in xfs_trans_ijoin()
36 if (ip->i_itemp == NULL) in xfs_trans_ijoin()
37 xfs_inode_item_init(ip, ip->i_mount); in xfs_trans_ijoin()
38 iip = ip->i_itemp; in xfs_trans_ijoin()
40 ASSERT(iip->ili_lock_flags == 0); in xfs_trans_ijoin()
41 iip->ili_lock_flags = lock_flags; in xfs_trans_ijoin()
42 ASSERT(!xfs_iflags_test(ip, XFS_ISTALE)); in xfs_trans_ijoin()
[all …]
|