Searched full:ipbrr0 (Results 1 – 5 of 5) sorted by relevance
5 determined by the TMU IP Block Revision Register (IPBRR0) at7 Table of correspondences between IPBRR0 values and example chips:
16 Register (IPBRR0) at offset 0x0BF8.17 Table of correspondences between IPBRR0 values and example chips:
45 IP Block Revision Register (IPBRR0) at offset 0x0BF8.47 Table of correspondences between IPBRR0 values and example136 Register (IPBRR0), at offset 0x0BF8, and Y is the Minor version
53 u32 ipbrr0; /* IP Block Revision Register 0 */ member