| /kernel/linux/linux-5.10/drivers/mailbox/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
6 on-chip processors through queued messages and interrupt driven
51 running on the Cortex-M3 rWTM secure processor of the Armada 37xx
77 This driver provides support for inter-processor communication
78 between CPU cores and MCU processor on Some Rockchip SOCs.
161 providing an interface for invoking the inter-process communication
162 signals from the application processor to other masters.
174 tristate "APM SoC X-Gene SLIMpro Mailbox Controller"
177 An implementation of the APM X-Gene Interprocessor Communication
178 Mailbox (IPCM) between the ARM 64-bit cores and SLIMpro controller.
[all …]
|
| /kernel/linux/linux-4.19/drivers/firmware/tegra/ |
| D | Kconfig | 7 IVC (Inter-VM Communication) protocol is part of the IPC
8 (Inter Processor Communication) framework on Tegra. It maintains the
17 BPMP (Boot and Power Management Processor) is designed to off-loading
|
| /kernel/linux/linux-5.10/drivers/firmware/tegra/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
8 IVC (Inter-VM Communication) protocol is part of the IPC
9 (Inter Processor Communication) framework on Tegra. It maintains the
18 BPMP (Boot and Power Management Processor) is designed to off-loading
|
| /kernel/linux/linux-4.19/drivers/mailbox/ |
| D | Kconfig | 5 on-chip processors through queued messages and interrupt driven
66 This driver provides support for inter-processor communication
67 between CPU cores and MCU processor on Some Rockchip SOCs.
150 providing an interface for invoking the inter-process communication
151 signals from the application processor to other masters.
163 tristate "APM SoC X-Gene SLIMpro Mailbox Controller"
166 An implementation of the APM X-Gene Interprocessor Communication
167 Mailbox (IPCM) between the ARM 64-bit cores and SLIMpro controller.
168 It is used to send short messages between ARM64-bit cores and
170 want to use the APM X-Gene SLIMpro IPCM support.
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mailbox/ |
| D | qcom-ipcc.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mailbox/qcom-ipcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. Inter-Processor Communication Controller
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
13 The Inter-Processor Communication Controller (IPCC) is a centralized hardware
14 to route interrupts across various subsystems. It involves a three-level
16 entity on the Application Processor Subsystem (APSS) that wants to listen to
18 a case, the client would be Modem (client-id is 2) and the signal would be
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/ |
| D | sifive,clint.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
19 The clock frequency of CLINT is specified via "timebase-frequency" DT
[all …]
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/powerpc/nintendo/ |
| D | wii.txt | 11 - model : Should be "nintendo,wii"
12 - compatible : Should be "nintendo,wii"
16 This node represents the multi-function "Hollywood" chip, which packages
21 - compatible : Should be "nintendo,hollywood"
25 Represents the interface between the graphics processor and a external
30 - compatible : should be "nintendo,hollywood-vi","nintendo,flipper-vi"
31 - reg : should contain the VI registers location and length
32 - interrupts : should contain the VI interrupt
34 1.b) The Processor Interface (PI) node
36 Represents the data and control interface between the main processor
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/powerpc/nintendo/ |
| D | wii.txt | 11 - model : Should be "nintendo,wii"
12 - compatible : Should be "nintendo,wii"
16 This node represents the multi-function "Hollywood" chip, which packages
21 - compatible : Should be "nintendo,hollywood"
25 Represents the interface between the graphics processor and a external
30 - compatible : should be "nintendo,hollywood-vi","nintendo,flipper-vi"
31 - reg : should contain the VI registers location and length
32 - interrupts : should contain the VI interrupt
34 1.b) The Processor Interface (PI) node
36 Represents the data and control interface between the main processor
[all …]
|
| /kernel/linux/linux-5.10/drivers/media/pci/cx18/ |
| D | cx18-scb.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 #include "cx18-mailbox.h"
14 /* NOTE: All ACK interrupts are in the SW2 register. All non-ACK interrupts
65 between SCB_OFFSET and SCB_OFFSET+SCB_RESERVED_SIZE-1 inclusive */
80 /* Offset where to find the Inter-Processor Communication data */
96 /* These fields form Inter-Processor Communication data which is used
102 /* bit 0: 1/0 processor ready/not ready. Set other bits to 0. */
|
| /kernel/linux/linux-4.19/drivers/media/pci/cx18/ |
| D | cx18-scb.h | 21 #include "cx18-mailbox.h"
23 /* NOTE: All ACK interrupts are in the SW2 register. All non-ACK interrupts
74 between SCB_OFFSET and SCB_OFFSET+SCB_RESERVED_SIZE-1 inclusive */
89 /* Offset where to find the Inter-Processor Communication data */
105 /* These fields form Inter-Processor Communication data which is used
111 /* bit 0: 1/0 processor ready/not ready. Set other bits to 0. */
|
| /kernel/linux/linux-5.10/arch/arc/kernel/ |
| D | smp.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 * -- Added support for Inter Processor Interrupts
9 * -- Initial Write (Borrowed heavily from ARM)
26 #include <asm/processor.h>
55 return -EINVAL; in arc_get_cpu_map()
58 return -EINVAL; in arc_get_cpu_map()
65 * "possible-cpus" property in DeviceTree pretend all [0..NR_CPUS-1] exist.
71 if (arc_get_cpu_map("possible-cpus", &cpumask)) { in arc_init_cpu_possible()
72 pr_warn("Failed to get possible-cpus from dtb, pretending all %u cpus exist\n", in arc_init_cpu_possible()
[all …]
|
| /kernel/linux/linux-4.19/arch/arc/kernel/ |
| D | smp.c | 2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
9 * -- Added support for Inter Processor Interrupts
12 * -- Initial Write (Borrowed heavily from ARM)
29 #include <asm/processor.h>
58 return -EINVAL; in arc_get_cpu_map()
61 return -EINVAL; in arc_get_cpu_map()
68 * "possible-cpus" property in DeviceTree pretend all [0..NR_CPUS-1] exist.
74 if (arc_get_cpu_map("possible-cpus", &cpumask)) { in arc_init_cpu_possible()
75 pr_warn("Failed to get possible-cpus from dtb, pretending all %u cpus exist\n", in arc_init_cpu_possible()
90 * - Initialise the CPU possible map early - this describes the CPUs
[all …]
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/mailbox/ |
| D | stm32-ipcc.txt | 1 * STMicroelectronics STM32 IPCC (Inter-Processor Communication Controller)
9 - compatible: Must be "st,stm32mp1-ipcc"
10 - reg: Register address range (base address and length)
11 - st,proc-id: Processor id using the mailbox (0 or 1)
12 - clocks: Input clock
13 - interrupt-names: List of names for the interrupts described by the interrupt
15 - "rx"
16 - "tx"
17 - "wakeup"
18 - interrupts: Interrupt specifiers for "rx channel occupied", "tx channel
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/misc/ |
| D | qcom,fastrpc.txt | 3 The FastRPC implements an IPC (Inter-Processor Communication)
6 to offload tasks to the DSP and free up the application processor for
9 - compatible:
14 - label
20 - #address-cells
25 - #size-cells
33 - All Compute context banks MUST contain the following properties:
35 - compatible:
38 Definition: must be "qcom,fastrpc-compute-cb"
40 - reg
[all …]
|
| /kernel/linux/linux-5.10/arch/ia64/include/asm/ |
| D | hw_irq.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (C) 2001-2003 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
23 * 1,3-14 are reserved from firmware
25 * 16-255 (vectored external interrupts) are available
37 #define AUTO_ASSIGN -1
42 * Vectors 0x10-0x1f are used for low priority interrupts, e.g. CMCI.
45 #define IA64_CMCP_VECTOR 0x1d /* corrected machine-check polling vector */
47 #define IA64_CMC_VECTOR 0x1f /* corrected machine-check interrupt vector */
49 * Vectors 0x20-0x2f are reserved for legacy ISA IRQs.
[all …]
|
| /kernel/linux/linux-4.19/arch/ia64/include/asm/ |
| D | hw_irq.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (C) 2001-2003 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
24 * 1,3-14 are reserved from firmware
26 * 16-255 (vectored external interrupts) are available
38 #define AUTO_ASSIGN -1
43 * Vectors 0x10-0x1f are used for low priority interrupts, e.g. CMCI.
46 #define IA64_CMCP_VECTOR 0x1d /* corrected machine-check polling vector */
48 #define IA64_CMC_VECTOR 0x1f /* corrected machine-check interrupt vector */
50 * Vectors 0x20-0x2f are reserved for legacy ISA IRQs.
[all …]
|
| /kernel/linux/linux-4.19/Documentation/virtual/kvm/devices/ |
| D | xics.txt | 11 sources, each identified by a 20-bit source number, and a set of
22 least-significant end of the word:
29 * Pending IPI (inter-processor interrupt) priority, 8 bits
35 * Current processor priority, 8 bits
43 bitfields, starting from the least-significant end of the word:
55 This bit is 1 for a level-sensitive interrupt source, or 0 for
56 edge-sensitive (or MSI).
60 regardless of its priority), for example by the ibm,int-off RTAS
|
| /kernel/linux/linux-5.10/drivers/media/platform/mtk-vcodec/ |
| D | venc_vpu_if.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
14 * struct venc_vpu_inst - encoder VPU driver instance
24 * @id: the id of inter-processor interrupt
|
| /kernel/linux/linux-5.10/include/linux/remoteproc/ |
| D | mtk_scp.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
17 * enum ipi_id - the id of inter-processor interrupt
|
| /kernel/linux/linux-4.19/arch/mips/kernel/ |
| D | smp-up.c | 6 * Copyright (C) 2006, 07 by Ralf Baechle (ralf@linux-mips.org)
14 * Send inter-processor interrupt
58 return -ENOSYS; in up_cpu_disable()
|
| /kernel/linux/linux-5.10/arch/mips/kernel/ |
| D | smp-up.c | 6 * Copyright (C) 2006, 07 by Ralf Baechle (ralf@linux-mips.org)
14 * Send inter-processor interrupt
58 return -ENOSYS; in up_cpu_disable()
|
| /kernel/linux/linux-4.19/drivers/media/platform/mtk-vcodec/ |
| D | venc_vpu_if.h | 23 * struct venc_vpu_inst - encoder VPU driver instance
33 * @id: the id of inter-processor interrupt
|
| /kernel/linux/linux-5.10/Documentation/virt/kvm/devices/ |
| D | xics.rst | 1 .. SPDX-License-Identifier: GPL-2.0
25 -EINVAL Value greater than KVM_MAX_VCPU_ID.
26 -EFAULT Invalid user pointer for attr->addr.
27 -EBUSY A vcpu is already connected to the device.
32 sources, each identified by a 20-bit source number, and a set of
43 least-significant end of the word:
50 * Pending IPI (inter-processor interrupt) priority, 8 bits
56 * Current processor priority, 8 bits
64 bitfields, starting from the least-significant end of the word:
79 This bit is 1 for a level-sensitive interrupt source, or 0 for
[all …]
|
| /kernel/linux/linux-5.10/Documentation/userspace-api/media/ |
| D | glossary.rst | 1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
45 **Digital Signal Processor**
51 **Field-programmable Gate Array**
56 See https://en.wikipedia.org/wiki/Field-programmable_gate_array.
65 together make a larger user-facing functional peripheral. For
73 **Inter-Integrated Circuit**
75 A multi-master, multi-slave, packet switched, single-ended,
77 like sub-device hardware components.
79 See http://www.nxp.com/docs/en/user-guide/UM10204.pdf.
101 **Image Signal Processor**
[all …]
|
| /kernel/linux/linux-5.10/drivers/media/platform/mtk-vpu/ |
| D | mtk_vpu.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Author: Andrew-CT Chen <andrew-ct.chen@mediatek.com>
13 * VPU (video processor unit) is a tiny processor controlling video hardware
23 * enum ipi_id - the id of inter-processor interrupt
65 * enum rst_id - reset id to register reset function for VPU watchdog timeout
80 * vpu_ipi_register - register an ipi function
96 * vpu_ipi_send - send data from AP to vpu.
103 * This function is thread-safe. When this function returns,
115 * vpu_get_plat_device - get VPU's platform device
126 * vpu_wdt_reg_handler - register a VPU watchdog handler
[all …]
|