Searched full:mmus (Results 1 – 25 of 53) sorted by relevance
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/iommu/ |
| D | samsung,sysmmu.txt | 3 Samsung's Exynos architecture contains System MMUs that enables scattered
13 System MMUs are in many to one relation with peripheral devices, i.e. single
14 peripheral device might have multiple System MMUs (usually one for each bus
20 MMUs.
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| D | ti,omap-iommu.txt | 28 instance number should be 0 for DSP MDMA MMUs and 1 for
29 DSP EDMA MMUs.
42 /* DRA74x DSP2 MMUs */
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/iommu/ |
| D | samsung,sysmmu.yaml | 13 Samsung's Exynos architecture contains System MMUs that enables scattered
23 System MMUs are in many to one relation with peripheral devices, i.e. single
24 peripheral device might have multiple System MMUs (usually one for each bus
30 MMUs.
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| D | ti,omap-iommu.txt | 28 instance number should be 0 for DSP MDMA MMUs and 1 for
29 DSP EDMA MMUs.
42 /* DRA74x DSP2 MMUs */
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| /kernel/linux/linux-5.10/drivers/gpu/drm/panfrost/ |
| D | panfrost_regs.h | 275 #define AS_COMMAND_UPDATE 0x01 /* Broadcasts the values in AS_TRANSTAB and ASn_MEMATTR to all MMUs…
276 #define AS_COMMAND_LOCK 0x02 /* Issue a lock region command to all MMUs */
277 #define AS_COMMAND_UNLOCK 0x03 /* Issue a flush region command to all MMUs */
278 #define AS_COMMAND_FLUSH 0x04 /* Flush all L2 caches then issue a flush region command to all MMUs
280 …e AS_COMMAND_FLUSH_PT 0x04 /* Flush all L2 caches then issue a flush region command to all MMUs */
282 flush all L2 caches then issue a flush region command to all MMUs */
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| /kernel/linux/linux-4.19/include/linux/ |
| D | mmu_notifier.h | 72 * accesses to the page through the secondary MMUs and not
419 * This is safe to start by updating the secondary MMUs, because the primary MMU
421 * set_pte_at_notify() has been invoked. Updating the secondary MMUs first is
424 * old page would remain mapped readonly in the secondary MMUs after the new
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| D | page-flags.h | 570 * through pmd_trans_huge, which in turn guarantees the secondary MMUs
572 * MMUs to call get_user_pages() only once for each compound page and
574 * MMU fault. If there will be a pmd split later, the secondary MMUs
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| /kernel/linux/linux-5.10/include/linux/ |
| D | mmu_notifier.h | 89 * accesses to the page through the secondary MMUs and not
623 * This is safe to start by updating the secondary MMUs, because the primary MMU
625 * set_pte_at_notify() has been invoked. Updating the secondary MMUs first is
628 * old page would remain mapped readonly in the secondary MMUs after the new
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| D | page-flags.h | 636 * through pmd_trans_huge, which in turn guarantees the secondary MMUs
638 * MMUs to call get_user_pages() only once for each compound page and
640 * MMU fault. If there will be a pmd split later, the secondary MMUs
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| /kernel/linux/linux-5.10/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/ |
| D | mmu_public.h | 53 /*! Invalidate the page table cache of all MMUs
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| /kernel/linux/linux-4.19/Documentation/arm64/ |
| D | booting.txt | 162 - Caches, MMUs
208 The requirements described above for CPU mode, caches, MMUs, architected
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| /kernel/linux/linux-4.19/arch/powerpc/mm/ |
| D | hugetlbpage-hash64.c | 3 * PPC64 Huge TLB Page Support for hash based MMUs (POWER4 and later)
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| D | hugepage-hash64.c | 16 * PPC64 THP Support for hash based MMUs
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| /kernel/linux/linux-5.10/Documentation/arm64/ |
| D | booting.rst | 173 - Caches, MMUs
273 The requirements described above for CPU mode, caches, MMUs, architected
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| /kernel/linux/linux-5.10/Documentation/translations/zh_CN/arm/ |
| D | Booting | 164 - 缓存，MMUs
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| /kernel/linux/linux-4.19/Documentation/translations/zh_CN/arm/ |
| D | Booting | 164 - 缓存，MMUs
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| /kernel/linux/linux-4.19/arch/sh/mm/ |
| D | Kconfig | 180 This enables 8kB pages as supported by SH-X2 and later MMUs.
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| /kernel/linux/linux-5.10/arch/powerpc/mm/book3s64/ |
| D | hash_hugetlbpage.c | 3 * PPC64 Huge TLB Page Support for hash based MMUs (POWER4 and later)
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| D | hash_hugepage.c | 16 * PPC64 THP Support for hash based MMUs
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| /kernel/linux/linux-5.10/arch/sh/mm/ |
| D | Kconfig | 175 This enables 8kB pages as supported by SH-X2 and later MMUs.
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| /kernel/linux/linux-5.10/arch/sh/include/asm/ |
| D | pgtable_32.h | 9 * notes on SH-X2 MMUs and 64-bit PTEs):
30 * SH-X2 MMUs and extended PTEs
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| /kernel/linux/linux-4.19/arch/sh/include/asm/ |
| D | pgtable_32.h | 9 * notes on SH-X2 MMUs and 64-bit PTEs):
30 * SH-X2 MMUs and extended PTEs
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| /kernel/linux/linux-5.10/arch/x86/kvm/mmu/ |
| D | spte.h | 100 * SPTEs used by MMUs without A/D bits are marked with SPTE_AD_DISABLED_MASK;
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| /kernel/linux/linux-4.19/drivers/gpu/drm/nouveau/ |
| D | nouveau_drm.c | 196 mmus[] = { in nouveau_cli_init() local
247 ret = nvif_mclass(&cli->device.object, mmus); in nouveau_cli_init()
253 ret = nvif_mmu_init(&cli->device.object, mmus[ret].oclass, &cli->mmu); in nouveau_cli_init()
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| /kernel/linux/linux-4.19/arch/mips/include/asm/ |
| D | page.h | 159 * On R4000-style MMUs where a TLB entry is mapping a adjacent even / odd
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