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/kernel/linux/linux-5.10/arch/x86/include/asm/uv/
Duv_mmrs.h555 unsigned long lb_hcerr:1; /* RW */
561 unsigned long lb_hcerr:1; /* RW */
563 unsigned long rh_hcerr:1; /* RW */
564 unsigned long lh0_hcerr:1; /* RW */
565 unsigned long lh1_hcerr:1; /* RW */
566 unsigned long gr0_hcerr:1; /* RW */
567 unsigned long gr1_hcerr:1; /* RW */
568 unsigned long ni0_hcerr:1; /* RW */
569 unsigned long ni1_hcerr:1; /* RW */
570 unsigned long lb_aoerr0:1; /* RW */
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/zydas/zd1211rw/
Dzd_rf_rf2959.c32 static int bits(u32 rw, int from, int to)
34 rw &= ~(0xffffffffU << (to+1));
35 rw >>= from;
36 return rw;
39 static int bit(u32 rw, int bit)
41 return bits(rw, bit, bit);
44 static void dump_regwrite(u32 rw)
46 int reg = bits(rw, 18, 22);
47 int rw_flag = bits(rw, 23, 23);
48 PDEBUG("rf2959 %#010x reg %d rw %d", rw, reg, rw_flag);
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/meson/
Dmeson_dw_hdmi.h12 * Bit 15-10: RW Reserved. Default 1 starting from G12A
13 * Bit 9 RW sw_reset_i2c starting from G12A
14 * Bit 8 RW sw_reset_axiarb starting from G12A
15 * Bit 7 RW Reserved. Default 1, sw_reset_emp starting from G12A
16 * Bit 6 RW Reserved. Default 1, sw_reset_flt starting from G12A
17 * Bit 5 RW Reserved. Default 1, sw_reset_hdcp22 starting from G12A
18 * Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset.
20 * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset;
23 * Bit 2 RW sw_reset_mem: KSV/REVOC mem. 1=Apply reset; 0=Release from reset.
25 * Bit 1 RW sw_reset_rnd: random number interface to HDCP. 1=Apply reset;
[all …]
/kernel/linux/linux-4.19/drivers/net/wireless/zydas/zd1211rw/
Dzd_rf_rf2959.c44 static int bits(u32 rw, int from, int to)
46 rw &= ~(0xffffffffU << (to+1));
47 rw >>= from;
48 return rw;
51 static int bit(u32 rw, int bit)
53 return bits(rw, bit, bit);
56 static void dump_regwrite(u32 rw)
58 int reg = bits(rw, 18, 22);
59 int rw_flag = bits(rw, 23, 23);
60 PDEBUG("rf2959 %#010x reg %d rw %d", rw, reg, rw_flag);
[all …]
/kernel/linux/linux-4.19/drivers/staging/mt7621-mmc/
Dmt6575_sd.h144 #define MSDC_CFG_MODE (0x1 << 0) /* RW */
145 #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */
146 #define MSDC_CFG_RST (0x1 << 2) /* RW */
147 #define MSDC_CFG_PIO (0x1 << 3) /* RW */
148 #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */
149 #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */
152 #define MSDC_CFG_CKDIV (0xff << 8) /* RW */
153 #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */
156 #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
157 #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/meson/
Dmeson_dw_hdmi.h24 * Bit 7 RW Reserved. Default 1.
25 * Bit 6 RW Reserved. Default 1.
26 * Bit 5 RW Reserved. Default 1.
27 * Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset.
29 * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset;
32 * Bit 2 RW sw_reset_mem: KSV/REVOC mem. 1=Apply reset; 0=Release from reset.
34 * Bit 1 RW sw_reset_rnd: random number interface to HDCP. 1=Apply reset;
36 * Bit 0 RW sw_reset_core: connects to IP's ~irstz. 1=Apply reset;
42 * Bit 12 RW i2s_ws_inv:1=Invert i2s_ws; 0=No invert. Default 0.
43 * Bit 11 RW i2s_clk_inv: 1=Invert i2s_clk; 0=No invert. Default 0.
[all …]
/kernel/linux/linux-4.19/arch/x86/include/asm/uv/
Duv_mmrs.h134 unsigned long enable:1; /* RW */
175 unsigned long vector_:8; /* RW */
176 unsigned long dm:3; /* RW */
177 unsigned long destmode:1; /* RW */
182 unsigned long m:1; /* RW */
184 unsigned long apic_id:32; /* RW */
623 unsigned long lb_hcerr:1; /* RW, W1C */
625 unsigned long rh_aoerr0:1; /* RW, W1C */
629 unsigned long lb_hcerr:1; /* RW */
631 unsigned long rh_hcerr:1; /* RW */
[all …]
/kernel/linux/linux-5.10/include/linux/mfd/
Dkhadas-mcu.h36 #define KHADAS_MCU_BOOT_MODE_REG 0x20 /* RW */
37 #define KHADAS_MCU_BOOT_EN_WOL_REG 0x21 /* RW */
38 #define KHADAS_MCU_BOOT_EN_RTC_REG 0x22 /* RW */
39 #define KHADAS_MCU_BOOT_EN_EXP_REG 0x23 /* RW */
40 #define KHADAS_MCU_BOOT_EN_IR_REG 0x24 /* RW */
41 #define KHADAS_MCU_BOOT_EN_DCIN_REG 0x25 /* RW */
42 #define KHADAS_MCU_BOOT_EN_KEY_REG 0x26 /* RW */
43 #define KHADAS_MCU_KEY_MODE_REG 0x27 /* RW */
44 #define KHADAS_MCU_LED_MODE_ON_REG 0x28 /* RW */
45 #define KHADAS_MCU_LED_MODE_OFF_REG 0x29 /* RW */
[all …]
Dstmfx.h16 #define STMFX_REG_SYS_CTRL 0x40 /* RW */
18 #define STMFX_REG_IRQ_OUT_PIN 0x41 /* RW */
19 #define STMFX_REG_IRQ_SRC_EN 0x42 /* RW */
21 #define STMFX_REG_IRQ_ACK 0x44 /* RW */
29 #define STMFX_REG_IRQ_GPI_SRC1 0x48 /* RW */
30 #define STMFX_REG_IRQ_GPI_SRC2 0x49 /* RW */
31 #define STMFX_REG_IRQ_GPI_SRC3 0x4A /* RW */
32 #define STMFX_REG_IRQ_GPI_EVT1 0x4C /* RW */
33 #define STMFX_REG_IRQ_GPI_EVT2 0x4D /* RW */
34 #define STMFX_REG_IRQ_GPI_EVT3 0x4E /* RW */
[all …]
/kernel/linux/linux-4.19/drivers/net/ethernet/intel/e1000e/
Dregs.h7 #define E1000_CTRL 0x00000 /* Device Control - RW */
9 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
10 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
11 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
12 #define E1000_FLA 0x0001C /* Flash Access - RW */
13 #define E1000_MDIC 0x00020 /* MDI Control - RW */
14 #define E1000_SCTL 0x00024 /* SerDes Control - RW */
15 #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
16 #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
17 #define E1000_FEXT 0x0002C /* Future Extended - RW */
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/intel/e1000e/
Dregs.h7 #define E1000_CTRL 0x00000 /* Device Control - RW */
9 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
10 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
11 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
12 #define E1000_FLA 0x0001C /* Flash Access - RW */
13 #define E1000_MDIC 0x00020 /* MDI Control - RW */
14 #define E1000_SCTL 0x00024 /* SerDes Control - RW */
15 #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
16 #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
17 #define E1000_FEXT 0x0002C /* Future Extended - RW */
[all …]
/kernel/linux/linux-4.19/arch/parisc/include/asm/
Dspinlock.h69 static __inline__ void arch_read_lock(arch_rwlock_t *rw) in arch_read_lock() argument
73 arch_spin_lock_flags(&rw->lock, flags); in arch_read_lock()
74 rw->counter++; in arch_read_lock()
75 arch_spin_unlock(&rw->lock); in arch_read_lock()
81 static __inline__ void arch_read_unlock(arch_rwlock_t *rw) in arch_read_unlock() argument
85 arch_spin_lock_flags(&rw->lock, flags); in arch_read_unlock()
86 rw->counter--; in arch_read_unlock()
87 arch_spin_unlock(&rw->lock); in arch_read_unlock()
93 static __inline__ int arch_read_trylock(arch_rwlock_t *rw) in arch_read_trylock() argument
98 if (arch_spin_trylock(&rw->lock)) { in arch_read_trylock()
[all …]
/kernel/linux/linux-4.19/drivers/gpu/drm/arm/
Dhdlcd_regs.h16 #define HDLCD_REG_INT_RAWSTAT 0x0010 /* rw */
18 #define HDLCD_REG_INT_MASK 0x0018 /* rw */
20 #define HDLCD_REG_FB_BASE 0x0100 /* rw */
21 #define HDLCD_REG_FB_LINE_LENGTH 0x0104 /* rw */
22 #define HDLCD_REG_FB_LINE_COUNT 0x0108 /* rw */
23 #define HDLCD_REG_FB_LINE_PITCH 0x010c /* rw */
24 #define HDLCD_REG_BUS_OPTIONS 0x0110 /* rw */
25 #define HDLCD_REG_V_SYNC 0x0200 /* rw */
26 #define HDLCD_REG_V_BACK_PORCH 0x0204 /* rw */
27 #define HDLCD_REG_V_DATA 0x0208 /* rw */
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/arm/
Dhdlcd_regs.h16 #define HDLCD_REG_INT_RAWSTAT 0x0010 /* rw */
18 #define HDLCD_REG_INT_MASK 0x0018 /* rw */
20 #define HDLCD_REG_FB_BASE 0x0100 /* rw */
21 #define HDLCD_REG_FB_LINE_LENGTH 0x0104 /* rw */
22 #define HDLCD_REG_FB_LINE_COUNT 0x0108 /* rw */
23 #define HDLCD_REG_FB_LINE_PITCH 0x010c /* rw */
24 #define HDLCD_REG_BUS_OPTIONS 0x0110 /* rw */
25 #define HDLCD_REG_V_SYNC 0x0200 /* rw */
26 #define HDLCD_REG_V_BACK_PORCH 0x0204 /* rw */
27 #define HDLCD_REG_V_DATA 0x0208 /* rw */
[all …]
/kernel/linux/linux-4.19/drivers/net/ethernet/intel/igb/
De1000_regs.h7 #define E1000_CTRL 0x00000 /* Device Control - RW */
9 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
10 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
11 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
12 #define E1000_MDIC 0x00020 /* MDI Control - RW */
13 #define E1000_MDICNFG 0x00E04 /* MDI Config - RW */
14 #define E1000_SCTL 0x00024 /* SerDes Control - RW */
15 #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
16 #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
17 #define E1000_FCT 0x00030 /* Flow Control Type - RW */
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/intel/igb/
De1000_regs.h7 #define E1000_CTRL 0x00000 /* Device Control - RW */
9 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
10 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
11 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
12 #define E1000_MDIC 0x00020 /* MDI Control - RW */
13 #define E1000_MDICNFG 0x00E04 /* MDI Config - RW */
14 #define E1000_SCTL 0x00024 /* SerDes Control - RW */
15 #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
16 #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
17 #define E1000_FCT 0x00030 /* Flow Control Type - RW */
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_reg.h12 * by size in bits. For example [RW 32]. The access types are:
15 * RW - Read/Write
32 /* [RW 1] Initiate the ATC array - reset all the valid bits */
38 /* [RW 5] Parity mask register #0 read/write */
44 /* [RW 19] Interrupt mask register #0 read/write */
48 /* [RW 4] Parity mask register #0 read/write */
54 /* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At
62 /* [RW 10] The number of free blocks below which the full signal to class 0
66 /* [RW 11] The number of free blocks above which the full signal to class 0
70 /* [RW 11] The number of free blocks below which the full signal to class 1
[all …]
/kernel/linux/linux-4.19/drivers/net/ethernet/broadcom/bnx2x/
Dbnx2x_reg.h12 * by size in bits. For example [RW 32]. The access types are:
15 * RW - Read/Write
32 /* [RW 1] Initiate the ATC array - reset all the valid bits */
38 /* [RW 5] Parity mask register #0 read/write */
44 /* [RW 19] Interrupt mask register #0 read/write */
48 /* [RW 4] Parity mask register #0 read/write */
54 /* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At
62 /* [RW 10] The number of free blocks below which the full signal to class 0
66 /* [RW 11] The number of free blocks above which the full signal to class 0
70 /* [RW 11] The number of free blocks below which the full signal to class 1
[all …]
/kernel/linux/linux-5.10/arch/ia64/include/asm/uv/
Duv_mmrs.h42 unsigned long vector_ : 8; /* RW */
43 unsigned long dm : 3; /* RW */
44 unsigned long destmode : 1; /* RW */
49 unsigned long m : 1; /* RW */
51 unsigned long apic_id : 32; /* RW */
178 unsigned long lb_hcerr : 1; /* RW, W1C */
179 unsigned long gr0_hcerr : 1; /* RW, W1C */
180 unsigned long gr1_hcerr : 1; /* RW, W1C */
181 unsigned long lh_hcerr : 1; /* RW, W1C */
182 unsigned long rh_hcerr : 1; /* RW, W1C */
[all …]
/kernel/linux/linux-4.19/arch/ia64/include/asm/uv/
Duv_mmrs.h42 unsigned long vector_ : 8; /* RW */
43 unsigned long dm : 3; /* RW */
44 unsigned long destmode : 1; /* RW */
49 unsigned long m : 1; /* RW */
51 unsigned long apic_id : 32; /* RW */
178 unsigned long lb_hcerr : 1; /* RW, W1C */
179 unsigned long gr0_hcerr : 1; /* RW, W1C */
180 unsigned long gr1_hcerr : 1; /* RW, W1C */
181 unsigned long lh_hcerr : 1; /* RW, W1C */
182 unsigned long rh_hcerr : 1; /* RW, W1C */
[all …]
/kernel/linux/linux-5.10/arch/parisc/include/asm/
Dspinlock.h67 static inline int arch_read_trylock(arch_rwlock_t *rw) in arch_read_trylock() argument
73 arch_spin_lock(&(rw->lock_mutex)); in arch_read_trylock()
79 if (rw->counter > 0) { in arch_read_trylock()
80 rw->counter--; in arch_read_trylock()
84 arch_spin_unlock(&(rw->lock_mutex)); in arch_read_trylock()
91 static inline int arch_write_trylock(arch_rwlock_t *rw) in arch_write_trylock() argument
97 arch_spin_lock(&(rw->lock_mutex)); in arch_write_trylock()
105 if (rw->counter == __ARCH_RW_LOCK_UNLOCKED__) { in arch_write_trylock()
106 rw->counter = 0; in arch_write_trylock()
109 arch_spin_unlock(&(rw->lock_mutex)); in arch_write_trylock()
[all …]
/kernel/linux/linux-4.19/Documentation/hwmon/
Damc682125 temp1_min rw "
26 temp1_max rw "
27 temp1_crit rw "
33 temp2_min rw "
34 temp2_max rw "
35 temp2_crit rw "
42 fan1_min rw "
43 fan1_max rw "
45 fan1_div rw Fan divisor can be either 2 or 4.
47 pwm1 rw pwm1
[all …]
/kernel/linux/linux-5.10/arch/arc/include/asm/
Dspinlock.h79 static inline void arch_read_lock(arch_rwlock_t *rw) in arch_read_lock() argument
87 * if (rw->counter > 0) { in arch_read_lock()
88 * rw->counter--; in arch_read_lock()
101 : [rwlock] "r" (&(rw->counter)), in arch_read_lock()
109 static inline int arch_read_trylock(arch_rwlock_t *rw) in arch_read_trylock() argument
125 : [rwlock] "r" (&(rw->counter)), in arch_read_trylock()
134 static inline void arch_write_lock(arch_rwlock_t *rw) in arch_write_lock() argument
144 * if (rw->counter == __ARCH_RW_LOCK_UNLOCKED__) { in arch_write_lock()
145 * rw->counter = 0; in arch_write_lock()
158 : [rwlock] "r" (&(rw->counter)), in arch_write_lock()
[all …]
/kernel/linux/linux-5.10/drivers/scsi/aic7xxx/
Daic79xx.reg101 access_mode RW
116 access_mode RW
133 access_mode RW
263 access_mode RW
281 access_mode RW
292 access_mode RW
302 access_mode RW
340 access_mode RW
350 access_mode RW
362 access_mode RW
[all …]
/kernel/linux/linux-4.19/drivers/scsi/aic7xxx/
Daic79xx.reg101 access_mode RW
116 access_mode RW
133 access_mode RW
263 access_mode RW
281 access_mode RW
292 access_mode RW
302 access_mode RW
340 access_mode RW
350 access_mode RW
362 access_mode RW
[all …]

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