| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/sound/ |
| D | rockchip,rk3328-codec.yaml | 65 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
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| /kernel/linux/linux-4.19/include/dt-bindings/clock/ |
| D | s3c2443.h | 36 #define SCLK_I2S1 19 macro
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| D | exynos7-clk.h | 120 #define SCLK_I2S1 25 macro
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| D | rk3188-cru-common.h | 41 #define SCLK_I2S1 76 macro
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| D | rk3128-cru.h | 38 #define SCLK_I2S1 81 macro
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| D | rk3228-cru.h | 37 #define SCLK_I2S1 81 macro
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| D | px30-cru.h | 22 #define SCLK_I2S1 20 macro
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| D | rv1108-cru.h | 35 #define SCLK_I2S1 76 macro
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| D | rk3328-cru.h | 40 #define SCLK_I2S1 42 macro
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| /kernel/linux/linux-5.10/include/dt-bindings/clock/ |
| D | s3c2443.h | 33 #define SCLK_I2S1 19 macro
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| D | exynos7-clk.h | 117 #define SCLK_I2S1 25 macro
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| D | rk3188-cru-common.h | 32 #define SCLK_I2S1 76 macro
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| D | rk3228-cru.h | 28 #define SCLK_I2S1 81 macro
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| D | rk3128-cru.h | 29 #define SCLK_I2S1 81 macro
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| D | rv1108-cru.h | 26 #define SCLK_I2S1 76 macro
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| D | px30-cru.h | 22 #define SCLK_I2S1 20 macro
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| D | rk3328-cru.h | 31 #define SCLK_I2S1 42 macro
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | exynos7-clock.txt | 87 - sclk_i2s1
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/clock/ |
| D | exynos7-clock.txt | 87 - sclk_i2s1
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| /kernel/linux/linux-5.10/drivers/clk/samsung/ |
| D | clk-s3c2443.c | 294 GATE(SCLK_I2S1, "sclk_i2s1", "div_i2s1", SCLKCON, 5, 0, 0),
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| D | clk-exynos7.c | 347 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_sclk_i2s1",
794 GATE(SCLK_I2S1, "sclk_i2s1_user", "sclk_i2s1",
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| /kernel/linux/linux-4.19/drivers/clk/samsung/ |
| D | clk-s3c2443.c | 335 GATE(SCLK_I2S1, "sclk_i2s1", "div_i2s1", SCLKCON, 5, 0, 0),
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| D | clk-exynos7.c | 351 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_sclk_i2s1",
793 GATE(SCLK_I2S1, "sclk_i2s1_user", "sclk_i2s1",
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| /kernel/linux/linux-5.10/drivers/clk/rockchip/ |
| D | clk-rk3128.c | 373 GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
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| /kernel/linux/linux-4.19/drivers/clk/rockchip/ |
| D | clk-rk3128.c | 381 GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
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