| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mmc/ |
| D | amlogic,meson-mx-sdhc.yaml | 4 $id: http://devicetree.org/schemas/mmc/amlogic,meson-mx-sdhc.yaml#
7 title: Amlogic Meson SDHC controller Device Tree Bindings
16 The SDHC MMC host controller on Amlogic SoCs provides an eMMC and MMC
24 - amlogic,meson8-sdhc
25 - amlogic,meson8b-sdhc
26 - amlogic,meson8m2-sdhc
27 - const: amlogic,meson-mx-sdhc
60 sdhc: mmc@8e00 {
61 compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc";
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| D | marvell,xenon-sdhci.txt | 6 Each SDHC is independent and owns independent resources, such as register sets,
8 Each SDHC should have an independent device tree node.
18 Array of clocks required for SDHC.
38 - marvell,xenon-sdhc-id:
39 Indicate the corresponding bit index of current SDHC in
40 SDHC System Operation Control Register Bit[7:0].
41 Set/clear the corresponding bit to enable/disable current SDHC.
42 If Xenon IP contains only one SDHC, this property is optional.
54 It doesn't stand for the entire SDHC type or property.
55 For example, "emmc 5.1 phy" doesn't mean that this Xenon SDHC only
[all …]
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| D | sdhci-msm.txt | 31 - CQE register map (Optional, CQE support is present on SDHC instance meant
63 - interconnect-names: For sdhc, we have two main paths.
64 1. Data path : sdhc to ddr
65 2. Config path : cpu to sdhc
67 is "sdhc-ddr" and for config interconnect path it is
68 "cpu-sdhc".
91 interconnect-names = "sdhc-ddr","cpu-sdhc";
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| D | vt8500-sdmmc.txt | 7 - compatible: Should be "wm,wm8505-sdhc".
15 sdhc@d800a000 {
16 compatible = "wm,wm8505-sdhc";
19 clocks = <&sdhc>;
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| D | sdhci-sirf.txt | 7 - compatible: sirf,prima2-sdhc
15 compatible = "sirf,prima2-sdhc";
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/mmc/ |
| D | marvell,xenon-sdhci.txt | 6 Each SDHC is independent and owns independent resources, such as register sets,
8 Each SDHC should have an independent device tree node.
18 Array of clocks required for SDHC.
38 - marvell,xenon-sdhc-id:
39 Indicate the corresponding bit index of current SDHC in
40 SDHC System Operation Control Register Bit[7:0].
41 Set/clear the corresponding bit to enable/disable current SDHC.
42 If Xenon IP contains only one SDHC, this property is optional.
54 It doesn't stand for the entire SDHC type or property.
55 For example, "emmc 5.1 phy" doesn't mean that this Xenon SDHC only
[all …]
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| D | vt8500-sdmmc.txt | 7 - compatible: Should be "wm,wm8505-sdhc".
15 sdhc@d800a000 {
16 compatible = "wm,wm8505-sdhc";
19 clocks = <&sdhc>;
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| D | sdhci-sirf.txt | 7 - compatible: sirf,prima2-sdhc
15 compatible = "sirf,prima2-sdhc";
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| /kernel/linux/linux-4.19/drivers/mmc/host/ |
| D | sdhci-xenon.c | 2 * Driver for Marvell Xenon SDHC as a platform device
61 /* Get the bit shift basing on the SDHC index */ in xenon_set_sdclk_off_idle()
84 /* Enable this SDHC */
102 /* Disable this SDHC */
409 * sdhc-id: the index of current SDHC.
428 if (!of_property_read_u32(np, "marvell,xenon-sdhc-id", &sdhc_id)) { in xenon_probe_dt()
432 dev_err(mmc_dev(mmc), "SDHC Index %d exceeds Number of SDHCs %d\n", in xenon_probe_dt()
459 /* Enable SDHC */ in xenon_sdhc_prepare()
482 /* disable SDHC */ in xenon_sdhc_unprepare()
692 MODULE_DESCRIPTION("SDHCI platform driver for Marvell Xenon SDHC");
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| D | sdhci-xenon.h | 14 /* Register Offset of Xenon SDHC self-defined register */
61 /* idx of SDHC */
79 * record the current ios setting of Xenon SDHC.
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| /kernel/linux/linux-5.10/drivers/mmc/host/ |
| D | sdhci-xenon.c | 3 * Driver for Marvell Xenon SDHC as a platform device
58 /* Get the bit shift basing on the SDHC index */ in xenon_set_sdclk_off_idle()
81 /* Enable this SDHC */
99 /* Disable this SDHC */
411 * sdhc-id: the index of current SDHC.
430 if (!of_property_read_u32(np, "marvell,xenon-sdhc-id", &sdhc_id)) { in xenon_probe_dt()
434 dev_err(mmc_dev(mmc), "SDHC Index %d exceeds Number of SDHCs %d\n", in xenon_probe_dt()
461 /* Enable SDHC */ in xenon_sdhc_prepare()
484 /* disable SDHC */ in xenon_sdhc_unprepare()
695 MODULE_DESCRIPTION("SDHCI platform driver for Marvell Xenon SDHC");
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| D | sdhci-xenon.h | 11 /* Register Offset of Xenon SDHC self-defined register */
58 /* idx of SDHC */
76 * record the current ios setting of Xenon SDHC.
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| D | Makefile | 71 meson-mx-sdhc-objs := meson-mx-sdhc-clkc.o meson-mx-sdhc-mmc.o
72 obj-$(CONFIG_MMC_MESON_MX_SDHC) += meson-mx-sdhc.o
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | meson8m2.dtsi | 87 &sdhc {
88 compatible = "amlogic,meson8m2-sdhc", "amlogic,meson-mx-sdhc";
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| D | wm8650.dtsi | 164 clksdhc: sdhc {
194 sdhc@d800a000 {
195 compatible = "wm,wm8505-sdhc";
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| /kernel/linux/linux-4.19/arch/powerpc/boot/dts/fsl/ |
| D | qoriq-esdhc-0.dtsi | 35 sdhc: sdhc@114000 { label
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| D | b4420si-pre.dtsi | 57 sdhc = &sdhc;
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| D | t102xsi-pre.dtsi | 59 sdhc = &sdhc;
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| /kernel/linux/linux-5.10/arch/powerpc/boot/dts/fsl/ |
| D | qoriq-esdhc-0.dtsi | 35 sdhc: sdhc@114000 { label
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| D | b4420si-pre.dtsi | 57 sdhc = &sdhc;
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| D | t102xsi-pre.dtsi | 59 sdhc = &sdhc;
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/clock/ |
| D | vt8500.txt | 66 sdhc: sdhc {
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | vt8500.txt | 66 sdhc: sdhc {
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| /kernel/linux/linux-4.19/arch/arm/boot/dts/ |
| D | wm8650.dtsi | 160 clksdhc: sdhc {
190 sdhc@d800a000 {
191 compatible = "wm,wm8505-sdhc";
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| /kernel/linux/linux-4.19/arch/arm/mach-imx/ |
| D | mach-armadillo5x0.c | 377 * SDHC 1
394 ret = gpio_request(gpio_det, "sdhc-card-detect"); in armadillo5x0_sdhc1_init()
400 ret = gpio_request(gpio_wp, "sdhc-write-protect"); in armadillo5x0_sdhc1_init()
409 "sdhc-detect", data); in armadillo5x0_sdhc1_init()
533 /* Register SDHC */ in armadillo5x0_late()
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