| /kernel/linux/linux-5.10/drivers/cpufreq/ |
| D | sa1110-cpufreq.c | 8 * 7 - SDRAM auto-power-up failure (rev A0)
10 * SDRAM reads (rev A0, B0, B1)
14 * The SDRAM type can be passed on the command line as cpu_sa1110.sdram=type
144 struct sdram_params *sdram) in sdram_calculate_timing() argument
152 * If SDCLK would invalidate the SDRAM timings, in sdram_calculate_timing()
158 if ((ns_to_cycles(sdram->tck, sd_khz) > 1) || in sdram_calculate_timing()
164 twr = ns_to_cycles(sdram->twr, mem_khz); in sdram_calculate_timing()
167 trp = ns_to_cycles(sdram->trp, mem_khz) - 1; in sdram_calculate_timing()
173 sd->mdcnfg |= sdram->cas_latency << 12; in sdram_calculate_timing()
174 sd->mdcnfg |= sdram->cas_latency << 28; in sdram_calculate_timing()
[all …]
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| /kernel/linux/linux-4.19/drivers/cpufreq/ |
| D | sa1110-cpufreq.c | 11 * 7 - SDRAM auto-power-up failure (rev A0)
13 * SDRAM reads (rev A0, B0, B1)
17 * The SDRAM type can be passed on the command line as cpu_sa1110.sdram=type
147 struct sdram_params *sdram) in sdram_calculate_timing() argument
155 * If SDCLK would invalidate the SDRAM timings, in sdram_calculate_timing()
161 if ((ns_to_cycles(sdram->tck, sd_khz) > 1) || in sdram_calculate_timing()
167 twr = ns_to_cycles(sdram->twr, mem_khz); in sdram_calculate_timing()
170 trp = ns_to_cycles(sdram->trp, mem_khz) - 1; in sdram_calculate_timing()
176 sd->mdcnfg |= sdram->cas_latency << 12; in sdram_calculate_timing()
177 sd->mdcnfg |= sdram->cas_latency << 28; in sdram_calculate_timing()
[all …]
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| /kernel/linux/linux-4.19/drivers/edac/ |
| D | altera_edac.h | 14 /* SDRAM Controller CtrlCfg Register */
17 /* SDRAM Controller CtrlCfg Register Bit Masks */
25 /* SDRAM Controller Address Width Register */
28 /* SDRAM Controller Address Widths Field Register */
38 /* SDRAM Controller Interface Data Width Register */
41 /* SDRAM Controller Interface Data Width Defines */
45 /* SDRAM Controller DRAM Status Register */
48 /* SDRAM Controller DRAM Status Register Bit Masks */
53 /* SDRAM Controller DRAM IRQ Register */
56 /* SDRAM Controller DRAM IRQ Register Bit Masks */
[all …]
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| D | r82600_edac.c | 33 /* Radisys say "The 82600 integrates a main memory SDRAM controller that
35 * sizes of 64 bit wide (72 bits with ECC) Synchronous DRAM (SDRAM) DIMMs,
39 * is not allowed. The 82600 SDRAM interface operates at the same frequency as
50 #define R82600_DRAMC 0x57 /* Various SDRAM related control bits
53 * 7 SDRAM ISA Hole Enable
58 * 2 SDRAM BIOS Flash Write Enable
59 * 1:0 SDRAM Refresh Rate: 00=Disabled
64 #define R82600_SDRAMC 0x76 /* "SDRAM Control Register"
65 * More SDRAM related control bits
70 * 7:5 Special SDRAM Mode Select
[all …]
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| /kernel/linux/linux-5.10/drivers/edac/ |
| D | altera_edac.h | 14 /* SDRAM Controller CtrlCfg Register */
17 /* SDRAM Controller CtrlCfg Register Bit Masks */
25 /* SDRAM Controller Address Width Register */
28 /* SDRAM Controller Address Widths Field Register */
38 /* SDRAM Controller Interface Data Width Register */
41 /* SDRAM Controller Interface Data Width Defines */
45 /* SDRAM Controller DRAM Status Register */
48 /* SDRAM Controller DRAM Status Register Bit Masks */
53 /* SDRAM Controller DRAM IRQ Register */
56 /* SDRAM Controller DRAM IRQ Register Bit Masks */
[all …]
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| D | r82600_edac.c | 33 /* Radisys say "The 82600 integrates a main memory SDRAM controller that
35 * sizes of 64 bit wide (72 bits with ECC) Synchronous DRAM (SDRAM) DIMMs,
39 * is not allowed. The 82600 SDRAM interface operates at the same frequency as
50 #define R82600_DRAMC 0x57 /* Various SDRAM related control bits
53 * 7 SDRAM ISA Hole Enable
58 * 2 SDRAM BIOS Flash Write Enable
59 * 1:0 SDRAM Refresh Rate: 00=Disabled
64 #define R82600_SDRAMC 0x76 /* "SDRAM Control Register"
65 * More SDRAM related control bits
70 * 7:5 Special SDRAM Mode Select
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/memory-controllers/ |
| D | mvebu-sdram-controller.txt | 1 Device Tree bindings for MVEBU SDRAM controllers
3 The Marvell EBU SoCs all have a SDRAM controller. The SDRAM controller
8 Armada XP SDRAM controller.
12 - compatible: for Armada XP, "marvell,armada-xp-sdram-controller"
14 include all SDRAM controller registers as per the datasheet.
19 compatible = "marvell,armada-xp-sdram-controller";
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/ |
| D | mvebu-sdram-controller.txt | 1 Device Tree bindings for MVEBU SDRAM controllers
3 The Marvell EBU SoCs all have a SDRAM controller. The SDRAM controller
8 Armada XP SDRAM controller.
12 - compatible: for Armada XP, "marvell,armada-xp-sdram-controller"
14 include all SDRAM controller registers as per the datasheet.
19 compatible = "marvell,armada-xp-sdram-controller";
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| /kernel/linux/linux-5.10/arch/arm/mach-pxa/include/mach/ |
| D | smemc.h | 15 #define MDCNFG (SMEMC_VIRT + 0x00) /* SDRAM Configuration Register 0 */
16 #define MDREFR (SMEMC_VIRT + 0x04) /* SDRAM Refresh Control Register */
21 #define SXLCR (SMEMC_VIRT + 0x18) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
30 #define MDMRS (SMEMC_VIRT + 0x40) /* MRS value to be written to SDRAM */
52 #define MDCNFG_DE0 (1 << 0) /* SDRAM Bank 0 Enable */
53 #define MDCNFG_DE1 (1 << 1) /* SDRAM Bank 1 Enable */
54 #define MDCNFG_DE2 (1 << 16) /* SDRAM Bank 2 Enable */
55 #define MDCNFG_DE3 (1 << 17) /* SDRAM Bank 3 Enable */
58 #define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
59 #define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
[all …]
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| /kernel/linux/linux-5.10/include/soc/at91/ |
| D | at91sam9_sdramc.h | 8 * SDRAM Controllers (SDRAMC) - System peripherals registers.
15 /* SDRAM Controller (SDRAMC) registers */
16 #define AT91_SDRAMC_MR 0x00 /* SDRAM Controller Mode Register */
26 #define AT91_SDRAMC_TR 0x04 /* SDRAM Controller Refresh Timer Register */
29 #define AT91_SDRAMC_CR 0x08 /* SDRAM Controller Configuration Register */
56 #define AT91_SDRAMC_LPR 0x10 /* SDRAM Controller Low Power Register */
70 #define AT91_SDRAMC_IER 0x14 /* SDRAM Controller Interrupt Enable Register */
71 #define AT91_SDRAMC_IDR 0x18 /* SDRAM Controller Interrupt Disable Register */
72 #define AT91_SDRAMC_IMR 0x1C /* SDRAM Controller Interrupt Mask Register */
73 #define AT91_SDRAMC_ISR 0x20 /* SDRAM Controller Interrupt Status Register */
[all …]
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| /kernel/linux/linux-4.19/arch/arm/mach-pxa/include/mach/ |
| D | smemc.h | 18 #define MDCNFG (SMEMC_VIRT + 0x00) /* SDRAM Configuration Register 0 */
19 #define MDREFR (SMEMC_VIRT + 0x04) /* SDRAM Refresh Control Register */
24 #define SXLCR (SMEMC_VIRT + 0x18) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
33 #define MDMRS (SMEMC_VIRT + 0x40) /* MRS value to be written to SDRAM */
55 #define MDCNFG_DE0 (1 << 0) /* SDRAM Bank 0 Enable */
56 #define MDCNFG_DE1 (1 << 1) /* SDRAM Bank 1 Enable */
57 #define MDCNFG_DE2 (1 << 16) /* SDRAM Bank 2 Enable */
58 #define MDCNFG_DE3 (1 << 17) /* SDRAM Bank 3 Enable */
61 #define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
62 #define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
[all …]
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| /kernel/linux/linux-4.19/include/soc/at91/ |
| D | at91sam9_sdramc.h | 7 * SDRAM Controllers (SDRAMC) - System peripherals registers.
19 /* SDRAM Controller (SDRAMC) registers */
20 #define AT91_SDRAMC_MR 0x00 /* SDRAM Controller Mode Register */
30 #define AT91_SDRAMC_TR 0x04 /* SDRAM Controller Refresh Timer Register */
33 #define AT91_SDRAMC_CR 0x08 /* SDRAM Controller Configuration Register */
60 #define AT91_SDRAMC_LPR 0x10 /* SDRAM Controller Low Power Register */
74 #define AT91_SDRAMC_IER 0x14 /* SDRAM Controller Interrupt Enable Register */
75 #define AT91_SDRAMC_IDR 0x18 /* SDRAM Controller Interrupt Disable Register */
76 #define AT91_SDRAMC_IMR 0x1C /* SDRAM Controller Interrupt Mask Register */
77 #define AT91_SDRAMC_ISR 0x20 /* SDRAM Controller Interrupt Status Register */
[all …]
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| /kernel/linux/linux-4.19/arch/arm/mach-ks8695/ |
| D | regs-mem.h | 30 #define KS8695_SDCON0 (0x30) /* SDRAM Control Register 0 */
31 #define KS8695_SDCON1 (0x34) /* SDRAM Control Register 1 */
32 #define KS8695_SDGCON (0x38) /* SDRAM General Control */
33 #define KS8695_SDBCON (0x3c) /* SDRAM Buffer Control */
34 #define KS8695_REFTIM (0x40) /* SDRAM Refresh Timer */
64 /* SDRAM Control Register */
71 /* SDRAM General Control Register */
75 /* SDRAM Buffer Control Register */
76 #define SDBCON_SDESTA (1 << 31) /* SDRAM Engine Status */
82 #define SDBCON_SDINI (3 << 16) /* SDRAM Initialization Control */
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/altera/ |
| D | socfpga-sdram-edac.txt | 1 Altera SOCFPGA SDRAM Error Detection & Correction [EDAC]
2 The EDAC accesses a range of registers in the SDRAM controller.
5 - compatible : should contain "altr,sdram-edac" or "altr,sdram-edac-a10"
7 - interrupts : Should contain the SDRAM ECC IRQ in the
12 compatible = "altr,sdram-edac";
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/altera/ |
| D | socfpga-sdram-edac.txt | 1 Altera SOCFPGA SDRAM Error Detection & Correction [EDAC]
2 The EDAC accesses a range of registers in the SDRAM controller.
5 - compatible : should contain "altr,sdram-edac" or "altr,sdram-edac-a10"
7 - interrupts : Should contain the SDRAM ECC IRQ in the
12 compatible = "altr,sdram-edac";
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/edac/ |
| D | aspeed-sdram-edac.txt | 14 - compatible: should be "aspeed,ast2500-sdram-edac"
15 - reg: sdram controller register set should be <0x1e6e0000 0x174>
21 edac: sdram@1e6e0000 {
22 compatible = "aspeed,ast2500-sdram-edac";
|
| /kernel/linux/linux-4.19/arch/arm/mach-pxa/ |
| D | sleep.S | 54 @ prepare SDRAM refresh settings
58 @ enable SDRAM self-refresh mode
95 @ prepare SDRAM refresh settings
99 @ enable SDRAM self-refresh mode
106 @ We keep the change-down close to the actual suspend on SDRAM
159 @ external accesses after SDRAM is put in self-refresh mode
165 @ put SDRAM into self-refresh
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| /kernel/linux/linux-5.10/arch/arm/mach-pxa/ |
| D | sleep.S | 54 @ prepare SDRAM refresh settings
58 @ enable SDRAM self-refresh mode
95 @ prepare SDRAM refresh settings
99 @ enable SDRAM self-refresh mode
106 @ We keep the change-down close to the actual suspend on SDRAM
159 @ external accesses after SDRAM is put in self-refresh mode
165 @ put SDRAM into self-refresh
|
| /kernel/linux/linux-5.10/drivers/net/usb/ |
| D | sr9700.h | 113 /* Tx sdram Write Pointer Address Low */
115 /* Tx sdram Write Pointer Address High */
117 /* Tx sdram Read Pointer Address Low */
119 /* Tx sdram Read Pointer Address High */
121 /* Rx sdram Write Pointer Address Low */
123 /* Rx sdram Write Pointer Address High */
125 /* Rx sdram Read Pointer Address Low */
127 /* Rx sdram Read Pointer Address High */
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| /kernel/linux/linux-4.19/drivers/net/usb/ |
| D | sr9700.h | 116 /* Tx sdram Write Pointer Address Low */
118 /* Tx sdram Write Pointer Address High */
120 /* Tx sdram Read Pointer Address Low */
122 /* Tx sdram Read Pointer Address High */
124 /* Rx sdram Write Pointer Address Low */
126 /* Rx sdram Write Pointer Address High */
128 /* Rx sdram Read Pointer Address Low */
130 /* Rx sdram Read Pointer Address High */
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| /kernel/linux/linux-5.10/arch/arm/mach-s3c/ |
| D | sleep-s3c2410.S | 38 orr r7, r7, #S3C2410_REFRESH_SELF @ SDRAM sleep command
39 orr r8, r8, #S3C2410_MISCCR_SDSLEEP @ SDRAM power-down signals
50 streq r7, [r4] @ SDRAM sleep command
51 streq r8, [r5] @ SDRAM power-down config
|
| /kernel/linux/linux-5.10/drivers/clk/sunxi-ng/ |
| D | ccu-sun9i-a80-de.c | 42 static SUNXI_CCU_GATE(dram_fe0_clk, "dram-fe0", "sdram",
44 static SUNXI_CCU_GATE(dram_fe1_clk, "dram-fe1", "sdram",
46 static SUNXI_CCU_GATE(dram_fe2_clk, "dram-fe2", "sdram",
48 static SUNXI_CCU_GATE(dram_deu0_clk, "dram-deu0", "sdram",
50 static SUNXI_CCU_GATE(dram_deu1_clk, "dram-deu1", "sdram",
52 static SUNXI_CCU_GATE(dram_be0_clk, "dram-be0", "sdram",
54 static SUNXI_CCU_GATE(dram_be1_clk, "dram-be1", "sdram",
56 static SUNXI_CCU_GATE(dram_be2_clk, "dram-be2", "sdram",
58 static SUNXI_CCU_GATE(dram_drc0_clk, "dram-drc0", "sdram",
60 static SUNXI_CCU_GATE(dram_drc1_clk, "dram-drc1", "sdram",
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| /kernel/linux/linux-4.19/drivers/clk/sunxi-ng/ |
| D | ccu-sun9i-a80-de.c | 50 static SUNXI_CCU_GATE(dram_fe0_clk, "dram-fe0", "sdram",
52 static SUNXI_CCU_GATE(dram_fe1_clk, "dram-fe1", "sdram",
54 static SUNXI_CCU_GATE(dram_fe2_clk, "dram-fe2", "sdram",
56 static SUNXI_CCU_GATE(dram_deu0_clk, "dram-deu0", "sdram",
58 static SUNXI_CCU_GATE(dram_deu1_clk, "dram-deu1", "sdram",
60 static SUNXI_CCU_GATE(dram_be0_clk, "dram-be0", "sdram",
62 static SUNXI_CCU_GATE(dram_be1_clk, "dram-be1", "sdram",
64 static SUNXI_CCU_GATE(dram_be2_clk, "dram-be2", "sdram",
66 static SUNXI_CCU_GATE(dram_drc0_clk, "dram-drc0", "sdram",
68 static SUNXI_CCU_GATE(dram_drc1_clk, "dram-drc1", "sdram",
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| /kernel/linux/linux-4.19/arch/arm/mach-s3c24xx/ |
| D | sleep-s3c2410.S | 39 orr r7, r7, #S3C2410_REFRESH_SELF @ SDRAM sleep command
40 orr r8, r8, #S3C2410_MISCCR_SDSLEEP @ SDRAM power-down signals
51 streq r7, [r4] @ SDRAM sleep command
52 streq r8, [r5] @ SDRAM power-down config
|
| /kernel/linux/linux-4.19/drivers/fpga/ |
| D | altera-fpga2sdram.c | 3 * FPGA to SDRAM Bridge Driver for Altera SoCFPGA Devices
9 * This driver manages a bridge between an FPGA and the SDRAM used by the ARM
13 * Reconfiguring these ports requires that no SDRAM transactions occur during
14 * reconfiguration. The code reconfiguring the ports cannot run out of SDRAM
15 * nor can the FPGA access the SDRAM during reconfiguration. This driver does
178 MODULE_DESCRIPTION("Altera SoCFPGA FPGA to SDRAM Bridge");
|