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/kernel/linux/linux-4.19/Documentation/devicetree/bindings/sram/
Dsunxi-sram.txt1 Allwinnner SoC SRAM controllers
4 The SRAM controller found on most Allwinner devices is represented by
5 a regular node for the SRAM controller itself, with sub-nodes
6 reprensenting the SRAM handled by the SRAM controller.
13 - "allwinner,sun4i-a10-sram-controller" (deprecated)
19 - "allwinner,sun50i-a64-sram-controller" (deprecated)
21 - reg : sram controller register offset + length
23 SRAM nodes
26 Each SRAM is described using the mmio-sram bindings documented in
27 Documentation/devicetree/bindings/sram/sram.txt
[all …]
Dsram.txt1 Generic on-chip SRAM
7 - compatible : mmio-sram or atmel,sama5d2-securam
9 - reg : SRAM iomem address range
11 Reserving sram areas:
14 Each child of the sram node specifies a region of reserved memory. Each
22 Required properties in the sram node:
26 within the sram to bus addresses
28 Optional properties in the sram node:
30 - no-memory-wc : the flag indicating, that SRAM memory region has not to
35 - reg : iomem address range, relative to the SRAM range
[all …]
Drockchip-smp-sram.txt1 Rockchip SRAM for smp bringup:
4 Rockchip's smp-capable SoCs use the first part of the sram for the bringup
6 residing at the very beginning of the sram.
8 Therefore a reserved section sub-node has to be added to the mmio-sram
12 - compatible : should be "rockchip,rk3066-smp-sram"
14 The rest of the properties should follow the generic mmio-sram discription
15 found in Documentation/devicetree/bindings/sram/sram.txt
19 sram: sram@10080000 {
20 compatible = "mmio-sram";
26 smp-sram@10080000 {
[all …]
Drenesas,smp-sram.txt1 * Renesas SMP SRAM
3 Renesas R-Car Gen2 and RZ/G1 SoCs need a small piece of SRAM for the jump stub
5 This memory is reserved by adding a child node to a "mmio-sram" node, cfr.
6 Documentation/devicetree/bindings/sram/sram.txt.
9 - compatible: Must be "renesas,smp-sram",
10 - reg: Address and length of the reserved SRAM.
16 icram1: sram@e63c0000 {
17 compatible = "mmio-sram";
23 smp-sram@0 {
24 compatible = "renesas,smp-sram";
Drockchip-pmu-sram.txt1 Rockchip SRAM for pmu:
4 The sram of pmu is used to store the function of resume from maskrom(the 1st
5 level loader). This is a common use of the "pmu-sram" because it keeps power
9 - compatible : should be "rockchip,rk3288-pmu-sram"
13 sram@ff720000 {
14 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/sram/
Dsram.yaml4 $id: http://devicetree.org/schemas/sram/sram.yaml#
7 title: Generic on-chip SRAM
15 Each child of the sram node specifies a region of reserved memory. Each
25 pattern: "^sram(@.*)?"
30 - mmio-sram
32 - rockchip,rk3288-pmu-sram
40 SRAM clock.
50 Should translate from local addresses within the sram to bus addresses.
54 The flag indicating, that SRAM memory region has not to be remapped
59 "^([a-z]*-)?sram(-section)?@[a-f0-9]+$":
[all …]
Dallwinner,sun4i-a10-system-control.yaml4 $id: http://devicetree.org/schemas/sram/allwinner,sun4i-a10-system-control.yaml#
14 The SRAM controller found on most Allwinner devices is represented
15 by a regular node for the SRAM controller itself, with sub-nodes
16 representing the SRAM handled by the SRAM controller.
27 - const: allwinner,sun4i-a10-sram-controller
42 - const: allwinner,sun50i-a64-sram-controller
59 "^sram@[a-z0-9]+":
64 const: mmio-sram
67 "^sram-section?@[a-f0-9]+$":
73 - const: allwinner,sun4i-a10-sram-a3-a4
[all …]
/kernel/linux/linux-5.10/drivers/misc/
Dsram.c3 * Generic on-chip SRAM allocation driver
21 #include "sram.h"
55 static int sram_add_pool(struct sram_dev *sram, struct sram_reserve *block, in sram_add_pool() argument
60 part->pool = devm_gen_pool_create(sram->dev, ilog2(SRAM_GRANULARITY), in sram_add_pool()
68 dev_err(sram->dev, "failed to register subpool: %d\n", ret); in sram_add_pool()
75 static int sram_add_export(struct sram_dev *sram, struct sram_reserve *block, in sram_add_export() argument
79 part->battr.attr.name = devm_kasprintf(sram->dev, GFP_KERNEL, in sram_add_export()
80 "%llx.sram", in sram_add_export()
90 return device_create_bin_file(sram->dev, &part->battr); in sram_add_export()
93 static int sram_add_partition(struct sram_dev *sram, struct sram_reserve *block, in sram_add_partition() argument
[all …]
/kernel/linux/linux-4.19/drivers/misc/
Dsram.c2 * Generic on-chip SRAM allocation driver
34 #include "sram.h"
68 static int sram_add_pool(struct sram_dev *sram, struct sram_reserve *block, in sram_add_pool() argument
73 part->pool = devm_gen_pool_create(sram->dev, ilog2(SRAM_GRANULARITY), in sram_add_pool()
81 dev_err(sram->dev, "failed to register subpool: %d\n", ret); in sram_add_pool()
88 static int sram_add_export(struct sram_dev *sram, struct sram_reserve *block, in sram_add_export() argument
92 part->battr.attr.name = devm_kasprintf(sram->dev, GFP_KERNEL, in sram_add_export()
93 "%llx.sram", in sram_add_export()
103 return device_create_bin_file(sram->dev, &part->battr); in sram_add_export()
106 static int sram_add_partition(struct sram_dev *sram, struct sram_reserve *block, in sram_add_partition() argument
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/sunxi/
Dsmp-sram.txt1 Allwinner SRAM for smp bringup:
4 Allwinner's A80 SoC uses part of the secure sram for hotplugging of the
9 Therefore a reserved section sub-node has to be added to the mmio-sram
12 Note that this is separate from the Allwinner SRAM controller found in
13 ../../sram/sunxi-sram.txt. This SRAM is secure only and not mappable to
17 check if this SRAM is usable first.
21 "allwinner,sun9i-a80-smp-sram"
23 The rest of the properties should follow the generic mmio-sram discription
24 found in ../../misc/sram.txt
28 sram_b: sram@20000 {
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/amlogic/
Dsmp-sram.txt1 Amlogic Meson8 and Meson8b SRAM for smp bringup:
4 Amlogic's SMP-capable SoCs use part of the sram for the bringup of the cores.
8 Therefore a reserved section sub-node has to be added to the mmio-sram
13 "amlogic,meson8-smp-sram"
14 "amlogic,meson8b-smp-sram"
16 The rest of the properties should follow the generic mmio-sram discription
17 found in ../../misc/sram.txt
21 sram: sram@d9000000 {
22 compatible = "mmio-sram";
28 smp-sram@1ff80 {
[all …]
/kernel/linux/linux-5.10/arch/arm/plat-omap/
Dsram.c3 * linux/arch/arm/plat-omap/sram.c
5 * OMAP SRAM detection and management
27 #include <plat/sram.h>
37 * Memory allocator for SRAM: calculates the new ceiling address
50 pr_err("Not enough space in SRAM\n"); in omap_sram_push_address()
63 void *sram; in omap_sram_push() local
68 sram = omap_sram_push_address(size); in omap_sram_push()
69 if (!sram) in omap_sram_push()
72 base = (unsigned long)sram & PAGE_MASK; in omap_sram_push()
77 dst = fncpy(sram, funcp, size); in omap_sram_push()
[all …]
/kernel/linux/linux-4.19/arch/arm/plat-omap/
Dsram.c2 * linux/arch/arm/plat-omap/sram.c
4 * OMAP SRAM detection and management
30 #include <plat/sram.h>
40 * Memory allocator for SRAM: calculates the new ceiling address
53 pr_err("Not enough space in SRAM\n"); in omap_sram_push_address()
66 void *sram; in omap_sram_push() local
71 sram = omap_sram_push_address(size); in omap_sram_push()
72 if (!sram) in omap_sram_push()
75 base = (unsigned long)sram & PAGE_MASK; in omap_sram_push()
80 dst = fncpy(sram, funcp, size); in omap_sram_push()
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/powerpc/fsl/
Dcache_sram.txt1 * Freescale PQ3 and QorIQ based Cache SRAM
5 as SRAM. This cache SRAM representation in the device
10 - compatible : should be "fsl,p2020-cache-sram"
11 - fsl,cache-sram-ctlr-handle : points to the L2 controller
12 - reg : offset and length of the cache-sram.
16 cache-sram@fff00000 {
17 fsl,cache-sram-ctlr-handle = <&L2>;
19 compatible = "fsl,p2020-cache-sram";
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/powerpc/fsl/
Dcache_sram.txt1 * Freescale PQ3 and QorIQ based Cache SRAM
5 as SRAM. This cache SRAM representation in the device
10 - compatible : should be "fsl,p2020-cache-sram"
11 - fsl,cache-sram-ctlr-handle : points to the L2 controller
12 - reg : offset and length of the cache-sram.
16 cache-sram@fff00000 {
17 fsl,cache-sram-ctlr-handle = <&L2>;
19 compatible = "fsl,p2020-cache-sram";
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dlpc4350.dtsi24 sram0: sram@10000000 {
25 compatible = "mmio-sram";
26 reg = <0x10000000 0x20000>; /* 96 + 32 KiB local SRAM */
29 sram1: sram@10080000 {
30 compatible = "mmio-sram";
31 reg = <0x10080000 0x12000>; /* 64 + 8 KiB local SRAM */
34 sram2: sram@20000000 {
35 compatible = "mmio-sram";
36 reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */
Dlpc4357.dtsi24 sram0: sram@10000000 {
25 compatible = "mmio-sram";
26 reg = <0x10000000 0x8000>; /* 32 KiB local SRAM */
29 sram1: sram@10080000 {
30 compatible = "mmio-sram";
31 reg = <0x10080000 0xa000>; /* 32 + 8 KiB local SRAM */
34 sram2: sram@20000000 {
35 compatible = "mmio-sram";
36 reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dlpc4350.dtsi24 sram0: sram@10000000 {
25 compatible = "mmio-sram";
26 reg = <0x10000000 0x20000>; /* 96 + 32 KiB local SRAM */
29 sram1: sram@10080000 {
30 compatible = "mmio-sram";
31 reg = <0x10080000 0x12000>; /* 64 + 8 KiB local SRAM */
34 sram2: sram@20000000 {
35 compatible = "mmio-sram";
36 reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */
Dlpc4357.dtsi24 sram0: sram@10000000 {
25 compatible = "mmio-sram";
26 reg = <0x10000000 0x8000>; /* 32 KiB local SRAM */
29 sram1: sram@10080000 {
30 compatible = "mmio-sram";
31 reg = <0x10080000 0xa000>; /* 32 + 8 KiB local SRAM */
34 sram2: sram@20000000 {
35 compatible = "mmio-sram";
36 reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */
/kernel/liteos_m/targets/riscv_nuclei_gd32vf103_soc_gcc/SoC/gd32vf103/Common/Include/
Dgd32vf103_exmc.h48 #define EXMC_SNCTL0 REG32(EXMC + 0x00U) /*!< EXMC SRAM/NOR flash co…
49 #define EXMC_SNTCFG0 REG32(EXMC + 0x04U) /*!< EXMC SRAM/NOR flash ti…
50 #define EXMC_SNWTCFG0 REG32(EXMC + 0x104U) /*!< EXMC SRAM/NOR flash wr…
72 /* EXMC NOR/SRAM timing initialize struct */
81 /* EXMC NOR/SRAM initialize struct */
84 …_region; /*!< select the region of EXMC NOR/SRAM bank */
96 … REG32(EXMC + 0x08U * (region)) /*!< EXMC SRAM/NOR flash control r…
97 …) REG32(EXMC + 0x04U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash timing co…
106 #define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */
110 /* EXMC NOR/SRAM bank region definition */
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-davinci/
Dsram.h3 * mach/sram.h - DaVinci simple SRAM allocator
10 /* ARBITRARY: SRAM allocations are multiples of this 2^N size */
14 * SRAM allocations return a CPU virtual address, or NULL on error.
15 * If a DMA address is requested and the SRAM supports DMA, its
18 * Errors include SRAM memory not being available, and requesting
19 * DMA mapped SRAM on systems which don't allow that.
/kernel/linux/linux-4.19/arch/arm/mach-davinci/
Dsram.h2 * mach/sram.h - DaVinci simple SRAM allocator
13 /* ARBITRARY: SRAM allocations are multiples of this 2^N size */
17 * SRAM allocations return a CPU virtual address, or NULL on error.
18 * If a DMA address is requested and the SRAM supports DMA, its
21 * Errors include SRAM memory not being available, and requesting
22 * DMA mapped SRAM on systems which don't allow that.
/kernel/linux/linux-5.10/drivers/mtd/devices/
Dms02-nv.h16 * 0x000000 - 0x3fffff SRAM
19 * Within the SRAM area the following ranges are forced by the system
28 * ID value is found, the firmware considers the SRAM clean, i.e.
38 * as well as the size of SRAM available, which can be 1MiB or 2MiB
44 * stored in the SRAM cannot be relied upon. But from the hardware
74 #define MS02NV_DIAG_TEST 0x01 /* SRAM test done (?) */
75 #define MS02NV_DIAG_RO 0x02 /* SRAM r/o test done */
76 #define MS02NV_DIAG_RW 0x04 /* SRAM r/w test done */
77 #define MS02NV_DIAG_FAIL 0x08 /* SRAM test failed */
78 #define MS02NV_DIAG_SIZE_MASK 0xf0 /* SRAM size mask */
[all …]
/kernel/linux/linux-4.19/drivers/mtd/devices/
Dms02-nv.h20 * 0x000000 - 0x3fffff SRAM
23 * Within the SRAM area the following ranges are forced by the system
32 * ID value is found, the firmware considers the SRAM clean, i.e.
42 * as well as the size of SRAM available, which can be 1MiB or 2MiB
48 * stored in the SRAM cannot be relied upon. But from the hardware
78 #define MS02NV_DIAG_TEST 0x01 /* SRAM test done (?) */
79 #define MS02NV_DIAG_RO 0x02 /* SRAM r/o test done */
80 #define MS02NV_DIAG_RW 0x04 /* SRAM r/w test done */
81 #define MS02NV_DIAG_FAIL 0x08 /* SRAM test failed */
82 #define MS02NV_DIAG_SIZE_MASK 0xf0 /* SRAM size mask */
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/crypto/
Dmv_cesa.txt9 region. Can also contain an entry for the SRAM attached to the CESA,
12 - reg-names: "regs". Can contain an "sram" entry, but this representation
17 - marvell,crypto-srams: phandle to crypto SRAM definitions
20 - marvell,crypto-sram-size: SRAM size reserved for crypto operations, if not
21 specified the whole SRAM is used (2KB)
31 marvell,crypto-sram-size = <0x600>;

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