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/kernel/linux/linux-5.10/arch/arm/mach-bcm/
Dplatsmp.c33 /* Name of device node property defining secondary boot register location */
34 #define OF_SECONDARY_BOOT "secondary-boot-reg"
91 pr_err("required secondary boot register not specified for CPU%u\n", in secondary_boot_addr_for()
120 /* Ensure the write is visible to the secondary core */ in nsp_write_lut()
141 * The ROM code has the secondary cores looping, waiting for an event.
143 * secondary boot register. When a core finds those bits contain its
147 * address back to the secondary boot register, and finally jumps to
151 * - Encode the (hardware) CPU id with the bottom bits of the secondary
153 * - Write that value into the secondary boot register.
154 * - Generate an event to wake up the secondary CPU(s).
[all …]
/kernel/linux/linux-4.19/Documentation/blockdev/drbd/
Dnode-states-8.dot2 Secondary -> Primary [ label = "ioctl_set_state()" ]
3 Primary -> Secondary [ label = "ioctl_set_state()" ]
7 Secondary -> Primary [ label = "recv state packet" ]
8 Primary -> Secondary [ label = "recv state packet" ]
10 Secondary -> Unknown [ label = "connection lost" ]
12 Unknown -> Secondary [ label = "connected" ]
/kernel/linux/linux-5.10/Documentation/admin-guide/blockdev/drbd/
Dnode-states-8.dot2 Secondary -> Primary [ label = "ioctl_set_state()" ]
3 Primary -> Secondary [ label = "ioctl_set_state()" ]
7 Secondary -> Primary [ label = "recv state packet" ]
8 Primary -> Secondary [ label = "recv state packet" ]
10 Secondary -> Unknown [ label = "connection lost" ]
12 Unknown -> Secondary [ label = "connected" ]
/kernel/linux/linux-4.19/arch/arm/mach-bcm/
Dplatsmp.c39 /* Name of device node property defining secondary boot register location */
40 #define OF_SECONDARY_BOOT "secondary-boot-reg"
97 pr_err("required secondary boot register not specified for CPU%u\n", in secondary_boot_addr_for()
126 /* Ensure the write is visible to the secondary core */ in nsp_write_lut()
147 * The ROM code has the secondary cores looping, waiting for an event.
149 * secondary boot register. When a core finds those bits contain its
153 * address back to the secondary boot register, and finally jumps to
157 * - Encode the (hardware) CPU id with the bottom bits of the secondary
159 * - Write that value into the secondary boot register.
160 * - Generate an event to wake up the secondary CPU(s).
[all …]
/kernel/linux/linux-5.10/arch/sparc/include/uapi/asm/
Dasi.h130 #define ASI_AIUS 0x11 /* Secondary, user */
132 #define ASI_AIUSL 0x19 /* Secondary, user, little endian */
134 #define ASI_S 0x81 /* Secondary, implicit */
136 #define ASI_SNF 0x83 /* Secondary, no fault */
138 #define ASI_SL 0x89 /* Secondary, implicit, l-endian */
140 #define ASI_SNFL 0x8b /* Secondary, no fault, l-endian */
161 * secondary, user
231 #define ASI_BLK_AIUS 0x71 /* Secondary, user, block ld/st */
242 #define ASI_BLK_AIUSL 0x79 /* Secondary, user, little, blk ld/st*/
255 #define ASI_PST8_S 0xc1 /* Secondary, 8 8-bit, partial */
[all …]
/kernel/linux/linux-4.19/arch/sparc/include/uapi/asm/
Dasi.h130 #define ASI_AIUS 0x11 /* Secondary, user */
132 #define ASI_AIUSL 0x19 /* Secondary, user, little endian */
134 #define ASI_S 0x81 /* Secondary, implicit */
136 #define ASI_SNF 0x83 /* Secondary, no fault */
138 #define ASI_SL 0x89 /* Secondary, implicit, l-endian */
140 #define ASI_SNFL 0x8b /* Secondary, no fault, l-endian */
161 * secondary, user
231 #define ASI_BLK_AIUS 0x71 /* Secondary, user, block ld/st */
242 #define ASI_BLK_AIUSL 0x79 /* Secondary, user, little, blk ld/st*/
255 #define ASI_PST8_S 0xc1 /* Secondary, 8 8-bit, partial */
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/bcm/
Dbrcm,nsp-cpu-method.txt3 This binding defines the enable method used for starting secondary
8 properties in the corresponding secondary "cpu" device tree node:
10 - secondary-boot-reg = <...>;
12 The secondary-boot-reg property is a u32 value that specifies the
14 entry point for a secondary CPU. This entry is cpu node specific
36 secondary-boot-reg = <0xffff042c>;
Dbrcm,bcm23550-cpu-method.txt3 This binding defines the enable method used for starting secondary
10 - secondary-boot-reg = <...>;
12 The secondary-boot-reg property is a u32 value that specifies the
14 code release a secondary CPU. The value written to the register is
34 secondary-boot-reg = <0x3500417c>;
Dbrcm,bcm11351-cpu-method.txt3 This binding defines the enable method used for starting secondary
10 - secondary-boot-reg = <...>;
12 The secondary-boot-reg property is a u32 value that specifies the
14 code release a secondary CPU. The value written to the register is
34 secondary-boot-reg = <0x3500417c>;
/kernel/linux/linux-5.10/arch/arm64/include/asm/
Dsmp.h20 /* Fatal system error detected by secondary CPU, crash the system */
70 * Called from the secondary holding pen, this is the secondary CPU entry point.
75 * Initial data for bringing up a secondary CPU.
76 * @stack - sp for the secondary CPU
77 * @status - Result passed back from the secondary CPU to
124 * The calling secondary CPU has detected serious configuration mismatch,
135 * If a secondary CPU enters the kernel but fails to come online,
/kernel/linux/linux-4.19/arch/arm64/include/asm/
Dsmp.h27 /* Fatal system error detected by secondary CPU, crash the system */
75 * Called from the secondary holding pen, this is the secondary CPU entry point.
80 * Initial data for bringing up a secondary CPU.
81 * @stack - sp for the secondary CPU
82 * @status - Result passed back from the secondary CPU to
129 * The calling secondary CPU has detected serious configuration mismatch,
140 * If a secondary CPU enters the kernel but fails to come online,
/kernel/linux/linux-4.19/Documentation/arm/Samsung/
DBootloader-interface.txt24 0x1c exynos4_secondary_startup Secondary CPU boot
25 0x1c + 4*cpu exynos4_secondary_startup (Exynos4412) Secondary CPU boot
36 0x00 exynos4_secondary_startup Secondary CPU boot
37 0x04 exynos4_secondary_startup (Exynos542x) Secondary CPU boot
38 4*cpu exynos4_secondary_startup (Exynos4412) Secondary CPU boot
49 0x0814 exynos4_secondary_startup (Exynos4210 r1.1) Secondary CPU boot
59 0x0908 Non-zero Secondary CPU boot up indicator
/kernel/linux/linux-4.19/drivers/ide/
Dide-generic.c43 static void ide_generic_check_pci_legacy_iobases(int *primary, int *secondary) in ide_generic_check_pci_legacy_iobases() argument
53 *secondary = 1; in ide_generic_check_pci_legacy_iobases()
59 *primary = *secondary = 1; in ide_generic_check_pci_legacy_iobases()
68 *secondary = 1; in ide_generic_check_pci_legacy_iobases()
81 int i, rc = 0, primary = 0, secondary = 0; in ide_generic_init() local
83 ide_generic_check_pci_legacy_iobases(&primary, &secondary); in ide_generic_init()
92 if (secondary == 0) in ide_generic_init()
/kernel/linux/linux-5.10/drivers/ide/
Dide-generic.c43 static void ide_generic_check_pci_legacy_iobases(int *primary, int *secondary) in ide_generic_check_pci_legacy_iobases() argument
53 *secondary = 1; in ide_generic_check_pci_legacy_iobases()
59 *primary = *secondary = 1; in ide_generic_check_pci_legacy_iobases()
68 *secondary = 1; in ide_generic_check_pci_legacy_iobases()
81 int i, rc = 0, primary = 0, secondary = 0; in ide_generic_init() local
83 ide_generic_check_pci_legacy_iobases(&primary, &secondary); in ide_generic_init()
92 if (secondary == 0) in ide_generic_init()
/kernel/linux/linux-4.19/sound/soc/qcom/qdsp6/
Dq6afe-dai.c464 {"Secondary MI2S Playback", NULL, "SEC_MI2S_RX"},
477 {"Secondary TDM0 Playback", NULL, "SEC_TDM_RX_0"},
478 {"Secondary TDM1 Playback", NULL, "SEC_TDM_RX_1"},
479 {"Secondary TDM2 Playback", NULL, "SEC_TDM_RX_2"},
480 {"Secondary TDM3 Playback", NULL, "SEC_TDM_RX_3"},
481 {"Secondary TDM4 Playback", NULL, "SEC_TDM_RX_4"},
482 {"Secondary TDM5 Playback", NULL, "SEC_TDM_RX_5"},
483 {"Secondary TDM6 Playback", NULL, "SEC_TDM_RX_6"},
484 {"Secondary TDM7 Playback", NULL, "SEC_TDM_RX_7"},
522 {"SEC_TDM_TX_0", NULL, "Secondary TDM0 Capture"},
[all …]
/kernel/linux/linux-4.19/Documentation/sparc/oradax/
Ddax-hv-api.txt172 [7:5] Secondary source address type
248 encoded data) and secondary data streams (meta-data for the encoded data).
260 … Variable width byte packed Data stream of lengths must be provided as a secondary
263 length encoding provided as a secondary input
267 as a secondary input
279 … a secondary input; pointer to the encoding table must be
291 … OZIP (CCB version 1) encoding as a secondary input; pointer to the encoding table must
296 … OZIP (CCB version 1) encoding stream of run lengths must be provided as a secondary
307 36.2.1.1.3. Secondary Input Format
309 …For primary input data streams which require a secondary input stream, the secondary input stream …
[all …]
/kernel/linux/linux-5.10/Documentation/sparc/oradax/
Ddax-hv-api.txt172 [7:5] Secondary source address type
248 encoded data) and secondary data streams (meta-data for the encoded data).
260 … Variable width byte packed Data stream of lengths must be provided as a secondary
263 length encoding provided as a secondary input
267 as a secondary input
279 … a secondary input; pointer to the encoding table must be
291 … OZIP (CCB version 1) encoding as a secondary input; pointer to the encoding table must
296 … OZIP (CCB version 1) encoding stream of run lengths must be provided as a secondary
307 36.2.1.1.3. Secondary Input Format
309 …For primary input data streams which require a secondary input stream, the secondary input stream …
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-mmp/
Dirqs.h180 /* secondary interrupt of INT #4 */
185 /* secondary interrupt of INT #5 */
190 /* secondary interrupt of INT #9 */
196 /* secondary interrupt of INT #17 */
204 /* secondary interrupt of INT #35 */
221 /* secondary interrupt of INT #51 */
226 /* secondary interrupt of INT #55 */
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/powerpc/fsl/
Dpamu.txt63 - fsl,secondary-cache-geometry
65 Two cells that specify the geometry of the secondary PAMU
108 fsl,secondary-cache-geometry = <128 2>;
114 fsl,secondary-cache-geometry = <128 2>;
120 fsl,secondary-cache-geometry = <128 2>;
126 fsl,secondary-cache-geometry = <128 2>;
132 fsl,secondary-cache-geometry = <128 2>;
/kernel/linux/linux-4.19/arch/arm/mach-mmp/
Dirqs.h180 /* secondary interrupt of INT #4 */
185 /* secondary interrupt of INT #5 */
190 /* secondary interrupt of INT #9 */
196 /* secondary interrupt of INT #17 */
204 /* secondary interrupt of INT #35 */
221 /* secondary interrupt of INT #51 */
226 /* secondary interrupt of INT #55 */
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/powerpc/fsl/
Dpamu.txt63 - fsl,secondary-cache-geometry
65 Two cells that specify the geometry of the secondary PAMU
108 fsl,secondary-cache-geometry = <128 2>;
114 fsl,secondary-cache-geometry = <128 2>;
120 fsl,secondary-cache-geometry = <128 2>;
126 fsl,secondary-cache-geometry = <128 2>;
132 fsl,secondary-cache-geometry = <128 2>;
/kernel/linux/linux-5.10/sound/soc/qcom/qdsp6/
Dq6afe-dai.c598 {"Secondary MI2S Playback", NULL, "SEC_MI2S_RX"},
611 {"Secondary TDM0 Playback", NULL, "SEC_TDM_RX_0"},
612 {"Secondary TDM1 Playback", NULL, "SEC_TDM_RX_1"},
613 {"Secondary TDM2 Playback", NULL, "SEC_TDM_RX_2"},
614 {"Secondary TDM3 Playback", NULL, "SEC_TDM_RX_3"},
615 {"Secondary TDM4 Playback", NULL, "SEC_TDM_RX_4"},
616 {"Secondary TDM5 Playback", NULL, "SEC_TDM_RX_5"},
617 {"Secondary TDM6 Playback", NULL, "SEC_TDM_RX_6"},
618 {"Secondary TDM7 Playback", NULL, "SEC_TDM_RX_7"},
656 {"SEC_TDM_TX_0", NULL, "Secondary TDM0 Capture"},
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-mvebu/
Dheadsmp.S2 * SMP support: Entry point for secondary CPUs
14 * This file implements the assembly entry point for secondary CPUs in
27 * Armada XP specific entry point for secondary CPUs.
28 * We add the CPU to the coherency fabric and then jump to secondary
/kernel/linux/linux-4.19/arch/arm/mach-mvebu/
Dheadsmp.S2 * SMP support: Entry point for secondary CPUs
14 * This file implements the assembly entry point for secondary CPUs in
27 * Armada XP specific entry point for secondary CPUs.
28 * We add the CPU to the coherency fabric and then jump to secondary
/kernel/linux/linux-5.10/arch/arm/mach-omap2/
Domap-headsmp.S3 * Secondary CPU startup routine source file.
21 /* Physical address needed since MMU not enabled yet on secondary core */
36 * OMAP5 specific entry point for secondary CPU to jump from ROM
38 * secondary core is held until we're ready for it to initialise.
75 * OMAP4 specific entry point for secondary CPU to jump from ROM
77 * secondary core is held until we're ready for it to initialise.

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