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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/
Dallwinner,sun8i-r40-tcon-top.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun8i-r40-tcon-top.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner R40 TCON TOP Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 TCON TOPs main purpose is to configure whole display pipeline. It
16 TCON for HDMI, muxes LCD and TV encoder GPIO output, selects TV
17 encoder clock source and contains additional TV TCON and DSI gates.
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/kernel/linux/linux-4.19/Documentation/devicetree/bindings/display/sunxi/
Dsun4i-drm.txt13 Frontend 0 [0] ------- [0] Backend 0 [0] ------- [0] TCON 0
14 [1] -- -- [1] [1] -- -- [1]
18 [0] -- -- [0] [0] -- -- [0]
19 Frontend 1 [1] ------- [1] Backend 1 [1] ------- [1] TCON 1
25 The same rule also applies to DE 2.0 mixer-TCON connections:
27 Mixer 0 [0] ----------- [0] TCON 0
28 [1] ---- ---- [1]
32 [0] ---- ---- [0]
33 Mixer 1 [1] ----------- [1] TCON 1
36 ------------
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/kernel/linux/linux-4.19/drivers/clk/sunxi-ng/
Dccu-sun8i-r40.c14 #include <linux/clk-provider.h>
31 #include "ccu-sun8i-r40.h"
43 .hw.init = CLK_HW_INIT("pll-cpu",
60 static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
69 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video0_clk, "pll-video0",
83 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
96 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
115 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
125 * The formula of pll-periph0 (1x) is 24MHz*N*K/2, and the formula
126 * of pll-periph0-sata is 24MHz*N*K/M/6, so the postdiv here is
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/kernel/linux/linux-5.10/drivers/clk/sunxi-ng/
Dccu-sun8i-r40.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
24 #include "ccu-sun8i-r40.h"
36 .hw.init = CLK_HW_INIT("pll-cpu",
48 * With sigma-delta modulation for fractional-N on the audio PLL,
62 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
72 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX(pll_video0_clk, "pll-video0",
87 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
100 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
119 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/allwinner/
Dsun50i-a64.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/sun50i-a64-ccu.h>
7 #include <dt-bindings/clock/sun8i-de2.h>
8 #include <dt-bindings/clock/sun8i-r-ccu.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/reset/sun50i-a64-ccu.h>
11 #include <dt-bindings/reset/sun8i-de2.h>
12 #include <dt-bindings/reset/sun8i-r-ccu.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
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/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dsunxi-h3-h5.dtsi4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/clock/sun8i-de2.h>
44 #include <dt-bindings/clock/sun8i-h3-ccu.h>
45 #include <dt-bindings/clock/sun8i-r-ccu.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/reset/sun8i-de2.h>
48 #include <dt-bindings/reset/sun8i-h3-ccu.h>
49 #include <dt-bindings/reset/sun8i-r-ccu.h>
52 interrupt-parent = <&gic>;
53 #address-cells = <1>;
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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dsunxi-h3-h5.dtsi4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/clock/sun8i-de2.h>
44 #include <dt-bindings/clock/sun8i-h3-ccu.h>
45 #include <dt-bindings/clock/sun8i-r-ccu.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/reset/sun8i-de2.h>
48 #include <dt-bindings/reset/sun8i-h3-ccu.h>
49 #include <dt-bindings/reset/sun8i-r-ccu.h>
52 interrupt-parent = <&gic>;
53 #address-cells = <1>;
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