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10 biology. Just because you have three numbers that describe the 'red',20 the human eye has color receptors that are sensitive to three different21 wavelengths of light. Hence the need to use three numbers to describe33 Since the human eye has only three color receptors it is perfectly67 A monitor or TV will reproduce colors by emitting light at three78 to define the three color primaries (these are typically defined as x, y80 reference: that is the color obtained when all three primaries are at86 Other colorspaces are defined by three chromaticity coordinates defined144 The colorspace definition itself consists of the three chromaticity
45 * - PRESENT *must* be in the bottom three bits because swap cache62 * 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still63 * hold protection values. That means the three protection bits are64 * reserved for both PTE and SWAP entry at the most significant three67 * There are three protection bits available for SWAP entry:71 * So those three bits have to be inside of 0-2nd LSB of PTE.
18 are no architectures which need more than three domain levels. The first40 Next three are schedule() statistics:50 Next three are statistics describing scheduling latency:119 Next three are active_load_balance() statistics:124 Next three are sched_balance_exec() statistics:129 Next three are sched_balance_fork() statistics:134 Next three are try_to_wake_up() statistics:144 the same information on a per-process level. There are three fields in
65 * SCU hardware requires that STP remote node entries take three consecutive66 * remote node index so the table is arranged in sets of three. The bits are67 * used as 0111 0111 to make a byte and the bits define the set of three remote151 * the remote nodes must occupy three consecutive remote node context153 * sets of three into a single nibble. When the STP RNi is allocated all162 * This field is the nibble selector for the above table. There are three164 * three remote node entries.
22 are no architectures which need more than three domain levels. The first45 Next three are schedule() statistics:57 Next three are statistics describing scheduling latency:126 Next three are active_load_balance() statistics:132 Next three are sched_balance_exec() statistics:138 Next three are sched_balance_fork() statistics:144 Next three are try_to_wake_up() statistics:155 the same information on a per-process level. There are three fields in
5 - #mux-control-cells : <0> if parallel (the three muxes are bound together6 with a single mux controller controlling all three muxes), or <1> if27 * Three independent mux controllers (of which one is used).53 * Three parallel muxes with one mux controller, useful e.g. if
37 (one internal, one external). EMC14x3 support three sensors (one internal,38 two external), and EMC14x4 support four sensors (one internal, three41 The chips implement three limits for each sensor: low (tempX_min), high46 all three limits.
57 (one internal, one external). EMC14x3 support three sensors (one internal,58 two external), and EMC14x4 support four sensors (one internal, three61 The chips implement three limits for each sensor: low (tempX_min), high66 all three limits.
72 .three = 0, \78 .three = arg->three, \86 var.three = 0; \199 unsigned long three; member208 int three; member216 u8 three; member224 char *three; member233 char __user *three; member
32 * 1. Three piecewise linear graphs (one for each plane) with three segments34 * each plane on the y axis. The three linear segments may have a different36 * a "Knee" point. As there are three such segments, four points need to be
4 The backlight brightness control operates at three different levels for the16 is at one of the three levels (daylight, office or dark). This29 one of the three levels (daylight, office or dark). This is an
4 The backlight brightness control operates at three different levels for the38 is at one of the three levels (daylight, office or dark). This52 one of the three levels (daylight, office or dark). This is an
4 The backlight brightness control operates at three different levels for the21 is at one of the three levels (daylight, office or dark). This35 one of the three levels (daylight, office or dark). This is an
7 CONFIG_DEBUG_LOCK_ALLOC -- Do three, covering CONFIG_PROVE_LOCKING & not.13 CONFIG_PREEMPT -- Do half. (First three and #8.)20 CONFIG_RCU_NOCB_CPU -- Do three, one with no rcu_nocbs CPUs, one with
7 CONFIG_DEBUG_LOCK_ALLOC -- Do three, covering CONFIG_PROVE_LOCKING & not.12 CONFIG_PREEMPT -- Do half. (First three and #8.)19 CONFIG_RCU_NOCB_CPU -- Do three, one with no rcu_nocbs CPUs, one with
13 * nodes, based on up to three entries per node for which the18 * of three memory map entries per node is "enough" entries for21 * to allow more than three entries per node or otherwise refine
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are19 required to have a HLIC with these three interrupt sources present. Since the29 RISC-V supervisor ISA manual, with only the following three interrupts being
46 be three modules called vpfe_capture.ko, vpss.ko and dm644x_ccdc.ko62 be three modules called vpfe_capture.ko, vpss.ko and dm355_ccdc.ko76 be three modules called vpfe_capture.ko, vpss.ko and isif.ko