Searched +full:u54 +full:- +full:mc +full:- +full:rvcoreip (Results 1 – 4 of 4) sorted by relevance
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/interrupt-controller/ |
| D | sifive,plic-1.0.0.txt | 1 SiFive Platform-Level Interrupt Controller (PLIC)
2 -------------------------------------------------
4 SiFive SOCs include an implementation of the Platform-Level Interrupt Controller
5 (PLIC) high-level specification in the RISC-V Privileged Architecture
10 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
13 Each interrupt can be enabled on per-context basis. Any context can claim
21 While the PLIC supports both edge-triggered and level-triggered interrupts,
23 specified in the PLIC device-tree binding.
25 While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
26 "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | sifive,plic-1.0.0.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SOCs include an implementation of the Platform-Level Interrupt Controller
12 (PLIC) high-level specification in the RISC-V Privileged Architecture
17 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
20 Each interrupt can be enabled on per-context basis. Any context can claim
28 While the PLIC supports both edge-triggered and level-triggered interrupts,
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| /kernel/linux/linux-4.19/drivers/irqchip/ |
| D | irq-sifive-plic.c | 1 // SPDX-License-Identifier: GPL-2.0
20 * This driver implements a version of the RISC-V PLIC with the actual layout
23 * https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf
25 * The largest number supported by devices marked as 'sifive,plic-1.0.0', is
26 * 1024, of which device 0 is defined as non-existent by the RISC-V Privileged
98 writel(enable, plic_regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID); in plic_irq_toggle()
102 if (handler->present) in plic_irq_toggle()
103 plic_toggle(handler->ctxid, d->hwirq, enable); in plic_irq_toggle()
144 * Handling an interrupt is a two-step process: first you claim the interrupt
152 void __iomem *claim = plic_hart_offset(handler->ctxid) + CONTEXT_CLAIM; in plic_handle_irq()
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| /kernel/linux/linux-5.10/drivers/irqchip/ |
| D | irq-sifive-plic.c | 1 // SPDX-License-Identifier: GPL-2.0
23 * This driver implements a version of the RISC-V PLIC with the actual layout
26 * https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf
28 * The largest number supported by devices marked as 'sifive,plic-1.0.0', is
29 * 1024, of which device 0 is defined as non-existent by the RISC-V Privileged
87 u32 __iomem *reg = handler->enable_base + (hwirq / 32) * sizeof(u32); in plic_toggle()
90 raw_spin_lock(&handler->enable_lock); in plic_toggle()
95 raw_spin_unlock(&handler->enable_lock); in plic_toggle()
104 writel(enable, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID); in plic_irq_toggle()
108 if (handler->present && in plic_irq_toggle()
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