| /kernel/linux/linux-5.10/sound/drivers/ |
| D | serial-u16550.c | 159 static inline void snd_uart16550_add_timer(struct snd_uart16550 *uart) in snd_uart16550_add_timer() argument
161 if (!uart->timer_running) { in snd_uart16550_add_timer()
163 mod_timer(&uart->buffer_timer, jiffies + (HZ + 255) / 256); in snd_uart16550_add_timer()
164 uart->timer_running = 1; in snd_uart16550_add_timer()
168 static inline void snd_uart16550_del_timer(struct snd_uart16550 *uart) in snd_uart16550_del_timer() argument
170 if (uart->timer_running) { in snd_uart16550_del_timer()
171 del_timer(&uart->buffer_timer); in snd_uart16550_del_timer()
172 uart->timer_running = 0; in snd_uart16550_del_timer()
177 static inline void snd_uart16550_buffer_output(struct snd_uart16550 *uart) in snd_uart16550_buffer_output() argument
179 unsigned short buff_out = uart->buff_out; in snd_uart16550_buffer_output()
[all …]
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| /kernel/linux/linux-4.19/sound/drivers/ |
| D | serial-u16550.c | 172 static inline void snd_uart16550_add_timer(struct snd_uart16550 *uart) in snd_uart16550_add_timer() argument
174 if (!uart->timer_running) { in snd_uart16550_add_timer()
176 mod_timer(&uart->buffer_timer, jiffies + (HZ + 255) / 256); in snd_uart16550_add_timer()
177 uart->timer_running = 1; in snd_uart16550_add_timer()
181 static inline void snd_uart16550_del_timer(struct snd_uart16550 *uart) in snd_uart16550_del_timer() argument
183 if (uart->timer_running) { in snd_uart16550_del_timer()
184 del_timer(&uart->buffer_timer); in snd_uart16550_del_timer()
185 uart->timer_running = 0; in snd_uart16550_del_timer()
190 static inline void snd_uart16550_buffer_output(struct snd_uart16550 *uart) in snd_uart16550_buffer_output() argument
192 unsigned short buff_out = uart->buff_out; in snd_uart16550_buffer_output()
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/serial/ |
| D | renesas,sci-serial.txt | 7 - "renesas,scif-r7s72100" for R7S72100 (RZ/A1H) SCIF compatible UART.
8 - "renesas,scif-r7s9210" for R7S9210 (RZ/A2) SCIF compatible UART.
9 - "renesas,scifa-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFA compatible UART.
10 - "renesas,scifb-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFB compatible UART.
11 - "renesas,scifa-r8a7740" for R8A7740 (R-Mobile A1) SCIFA compatible UART.
12 - "renesas,scifb-r8a7740" for R8A7740 (R-Mobile A1) SCIFB compatible UART.
13 - "renesas,scif-r8a7743" for R8A7743 (RZ/G1M) SCIF compatible UART.
14 - "renesas,scifa-r8a7743" for R8A7743 (RZ/G1M) SCIFA compatible UART.
15 - "renesas,scifb-r8a7743" for R8A7743 (RZ/G1M) SCIFB compatible UART.
16 - "renesas,hscif-r8a7743" for R8A7743 (RZ/G1M) HSCIF compatible UART.
[all …]
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| D | mvebu-uart.txt | 1 * Marvell UART : Non standard UART used in some of Marvell EBU SoCs
6 - "marvell,armada-3700-uart" for the standard variant of the UART
9 - "marvell,armada-3700-uart-ext" for the extended variant of the
10 UART (128 bytes FIFO, DMA, front interrupts, 8-bit or 32-bit
13 - clocks: UART reference clock used to derive the baudrate. If no clock
14 is provided (possible only with the "marvell,armada-3700-uart"
20 (marvell,armada-3700-uart): "uart-sum", "uart-tx" and "uart-rx",
21 respectively the UART sum interrupt, the UART TX interrupt and
22 UART RX interrupt. A corresponding interrupt-names property must
25 (marvell,armada-3700-uart-ext): "uart-tx" and "uart-rx",
[all …]
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| D | mtk-uart.txt | 1 * Mediatek Universal Asynchronous Receiver/Transmitter (UART)
5 * "mediatek,mt2701-uart" for MT2701 compatible UARTS
6 * "mediatek,mt2712-uart" for MT2712 compatible UARTS
7 * "mediatek,mt6580-uart" for MT6580 compatible UARTS
8 * "mediatek,mt6582-uart" for MT6582 compatible UARTS
9 * "mediatek,mt6589-uart" for MT6589 compatible UARTS
10 * "mediatek,mt6755-uart" for MT6755 compatible UARTS
11 * "mediatek,mt6765-uart" for MT6765 compatible UARTS
12 * "mediatek,mt6795-uart" for MT6795 compatible UARTS
13 * "mediatek,mt6797-uart" for MT6797 compatible UARTS
[all …]
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| D | sirf-uart.txt | 4 - compatible : Should be "sirf,prima2-uart", "sirf, prima2-usp-uart",
5 "sirf,atlas7-uart" or "sirf,atlas7-usp-uart".
7 - interrupts : Should contain uart interrupt
9 - clocks : Should contain uart clock number
12 - uart-has-rtscts: we have hardware flow controller pins in hardware
13 - rts-gpios: RTS pin for USP-based UART if uart-has-rtscts is true
14 - cts-gpios: CTS pin for USP-based UART if uart-has-rtscts is true
18 uart0: uart@b0050000 {
20 compatible = "sirf,prima2-uart";
30 compatible = "sirf,prima2-usp-uart";
[all …]
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| /kernel/liteos_m/targets/riscv_nuclei_demo_soc_gcc/SoC/demosoc/Common/Source/Drivers/ |
| D | demosoc_uart.c | 4 int32_t uart_init(UART_TypeDef* uart, uint32_t baudrate) in uart_init() argument
6 if (__RARELY(uart == NULL)) { in uart_init()
9 uart->DIV = SystemCoreClock / baudrate - 1; in uart_init()
10 uart->TXCTRL |= UART_TXEN; in uart_init()
11 uart->RXCTRL |= UART_RXEN; in uart_init()
15 int32_t uart_config_stopbit(UART_TypeDef* uart, UART_STOP_BIT stopbit) in uart_config_stopbit() argument
17 if (__RARELY(uart == NULL)) { in uart_config_stopbit()
22 uart->TXCTRL &= stopval | (~UART_TXCTRL_TXCNT_MASK); in uart_config_stopbit()
26 int32_t uart_write(UART_TypeDef* uart, uint8_t val) in uart_write() argument
28 if (__RARELY(uart == NULL)) { in uart_write()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/serial/ |
| D | fsl-imx-uart.yaml | 4 $id: http://devicetree.org/schemas/serial/fsl-imx-uart.yaml#
7 title: Freescale i.MX Universal Asynchronous Receiver/Transmitter (UART)
19 - const: fsl,imx1-uart
20 - const: fsl,imx21-uart
23 - fsl,imx25-uart
24 - fsl,imx27-uart
25 - fsl,imx31-uart
26 - fsl,imx35-uart
27 - fsl,imx50-uart
28 - fsl,imx51-uart
[all …]
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| D | mvebu-uart.txt | 1 * Marvell UART : Non standard UART used in some of Marvell EBU SoCs
6 - "marvell,armada-3700-uart" for the standard variant of the UART
9 - "marvell,armada-3700-uart-ext" for the extended variant of the
10 UART (128 bytes FIFO, DMA, front interrupts, 8-bit or 32-bit
13 - clocks: UART reference clock used to derive the baudrate. If no clock
14 is provided (possible only with the "marvell,armada-3700-uart"
20 (marvell,armada-3700-uart): "uart-sum", "uart-tx" and "uart-rx",
21 respectively the UART sum interrupt, the UART TX interrupt and
22 UART RX interrupt. A corresponding interrupt-names property must
25 (marvell,armada-3700-uart-ext): "uart-tx" and "uart-rx",
[all …]
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| D | mtk-uart.txt | 1 * MediaTek Universal Asynchronous Receiver/Transmitter (UART)
5 * "mediatek,mt2701-uart" for MT2701 compatible UARTS
6 * "mediatek,mt2712-uart" for MT2712 compatible UARTS
7 * "mediatek,mt6580-uart" for MT6580 compatible UARTS
8 * "mediatek,mt6582-uart" for MT6582 compatible UARTS
9 * "mediatek,mt6589-uart" for MT6589 compatible UARTS
10 * "mediatek,mt6755-uart" for MT6755 compatible UARTS
11 * "mediatek,mt6765-uart" for MT6765 compatible UARTS
12 * "mediatek,mt6779-uart" for MT6779 compatible UARTS
13 * "mediatek,mt6795-uart" for MT6795 compatible UARTS
[all …]
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| D | snps-dw-apb-uart.yaml | 4 $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
7 title: Synopsys DesignWare ABP UART
20 - renesas,r9a06g032-uart
21 - renesas,r9a06g033-uart
22 - const: renesas,rzn1-uart
25 - rockchip,px30-uart
26 - rockchip,rk3036-uart
27 - rockchip,rk3066-uart
28 - rockchip,rk3188-uart
29 - rockchip,rk3288-uart
[all …]
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| D | 8250.yaml | 7 title: UART (Universal Asynchronous Receiver/Transmitter) bindings
24 const: mrvl,mmp-uart
56 - const: intel,xscale-uart
57 - const: mrvl,pxa-uart
58 - const: nuvoton,npcm750-uart
59 - const: nvidia,tegra20-uart
60 - const: nxp,lpc3220-uart
69 - nxp,lpc1850-uart
71 - ti,da830-uart
76 - cavium,octeon-3860-uart
[all …]
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| D | sirf-uart.txt | 4 - compatible : Should be "sirf,prima2-uart", "sirf, prima2-usp-uart",
5 "sirf,atlas7-uart" or "sirf,atlas7-usp-uart".
7 - interrupts : Should contain uart interrupt
9 - clocks : Should contain uart clock number
12 - uart-has-rtscts: we have hardware flow controller pins in hardware
13 - rts-gpios: RTS pin for USP-based UART if uart-has-rtscts is true
14 - cts-gpios: CTS pin for USP-based UART if uart-has-rtscts is true
18 uart0: uart@b0050000 {
20 compatible = "sirf,prima2-uart";
30 compatible = "sirf,prima2-usp-uart";
[all …]
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| D | samsung_uart.yaml | 7 title: Samsung S3C, S5P and Exynos SoC UART Controller
14 Each Samsung UART should have an alias correctly numbered in the "aliases"
22 - samsung,s3c2410-uart
23 - samsung,s3c2412-uart
24 - samsung,s3c2440-uart
25 - samsung,s3c6400-uart
26 - samsung,s5pv210-uart
27 - samsung,exynos4210-uart
48 - const: uart
59 samsung,uart-fifosize:
[all …]
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| /kernel/linux/linux-5.10/drivers/tty/serial/ |
| D | men_z135_uart.c | 3 * MEN 16z135 High Speed UART
132 * @uart: The UART port
136 static inline void men_z135_reg_set(struct men_z135_port *uart, in men_z135_reg_set() argument
139 struct uart_port *port = &uart->port; in men_z135_reg_set()
143 spin_lock_irqsave(&uart->lock, flags); in men_z135_reg_set()
149 spin_unlock_irqrestore(&uart->lock, flags); in men_z135_reg_set()
154 * @uart: The UART port
158 static void men_z135_reg_clr(struct men_z135_port *uart, in men_z135_reg_clr() argument
161 struct uart_port *port = &uart->port; in men_z135_reg_clr()
165 spin_lock_irqsave(&uart->lock, flags); in men_z135_reg_clr()
[all …]
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| D | timbuart.c | 3 * timbuart.c timberdale FPGA UART driver
8 * Timberdale FPGA UART
55 struct timbuart_port *uart = in timbuart_start_tx() local
59 tasklet_schedule(&uart->tasklet); in timbuart_start_tx()
121 struct timbuart_port *uart = in timbuart_handle_tx_port() local
140 *ier |= uart->last_ier & TXFLAGS; in timbuart_handle_tx_port()
177 struct timbuart_port *uart = from_tasklet(uart, t, tasklet); in timbuart_tasklet() local
180 spin_lock(&uart->port.lock); in timbuart_tasklet()
182 isr = ioread32(uart->port.membase + TIMBUART_ISR); in timbuart_tasklet()
183 dev_dbg(uart->port.dev, "%s ISR: %x\n", __func__, isr); in timbuart_tasklet()
[all …]
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| /kernel/linux/linux-4.19/drivers/tty/serial/ |
| D | men_z135_uart.c | 3 * MEN 16z135 High Speed UART
132 * @uart: The UART port
136 static inline void men_z135_reg_set(struct men_z135_port *uart, in men_z135_reg_set() argument
139 struct uart_port *port = &uart->port; in men_z135_reg_set()
143 spin_lock_irqsave(&uart->lock, flags); in men_z135_reg_set()
149 spin_unlock_irqrestore(&uart->lock, flags); in men_z135_reg_set()
154 * @uart: The UART port
158 static void men_z135_reg_clr(struct men_z135_port *uart, in men_z135_reg_clr() argument
161 struct uart_port *port = &uart->port; in men_z135_reg_clr()
165 spin_lock_irqsave(&uart->lock, flags); in men_z135_reg_clr()
[all …]
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| D | timbuart.c | 3 * timbuart.c timberdale FPGA UART driver
8 * Timberdale FPGA UART
55 struct timbuart_port *uart = in timbuart_start_tx() local
59 tasklet_schedule(&uart->tasklet); in timbuart_start_tx()
121 struct timbuart_port *uart = in timbuart_handle_tx_port() local
140 *ier |= uart->last_ier & TXFLAGS; in timbuart_handle_tx_port()
177 struct timbuart_port *uart = (struct timbuart_port *)arg; in timbuart_tasklet() local
180 spin_lock(&uart->port.lock); in timbuart_tasklet()
182 isr = ioread32(uart->port.membase + TIMBUART_ISR); in timbuart_tasklet()
183 dev_dbg(uart->port.dev, "%s ISR: %x\n", __func__, isr); in timbuart_tasklet()
[all …]
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| /kernel/linux/linux-5.10/drivers/tty/serial/8250/ |
| D | 8250_tegra.c | 44 struct tegra_uart *uart; in tegra_uart_probe() local
49 uart = devm_kzalloc(&pdev->dev, sizeof(*uart), GFP_KERNEL); in tegra_uart_probe()
50 if (!uart) in tegra_uart_probe()
89 uart->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL); in tegra_uart_probe()
90 if (IS_ERR(uart->rst)) in tegra_uart_probe()
91 return PTR_ERR(uart->rst); in tegra_uart_probe()
95 uart->clk = devm_clk_get(&pdev->dev, NULL); in tegra_uart_probe()
96 if (IS_ERR(uart->clk)) { in tegra_uart_probe()
101 ret = clk_prepare_enable(uart->clk); in tegra_uart_probe()
105 port->uartclk = clk_get_rate(uart->clk); in tegra_uart_probe()
[all …]
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| D | 8250_core.c | 286 * IIR bits on their UART, but it's specifically designed for in serial8250_backup_timeout()
287 * the "Diva" UART used on the management processor on many HP in serial8250_backup_timeout()
595 * Check whether an invalid uart number has been specified, and in univ8250_console_setup()
627 * console=uart[8250],io|mmio|mmio16|mmio32,<addr>[,<options>]
628 * console=uart[8250],0x<addr>[,<options>]
640 char match[] = "uart"; /* 8250-specific earlycon name */ in univ8250_console_match()
808 struct uart_8250_port uart; in serial8250_probe() local
811 memset(&uart, 0, sizeof(uart)); in serial8250_probe()
817 uart.port.iobase = p->iobase; in serial8250_probe()
818 uart.port.membase = p->membase; in serial8250_probe()
[all …]
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| /kernel/linux/linux-5.10/arch/mips/kernel/ |
| D | cps-vec-ns16550.S | 32 * _mips_cps_putc() - write a character to the UART
34 * @t9: UART base address
45 * _mips_cps_puts() - write a string to the UART
47 * @t9: UART base address
49 * Write a null-terminated ASCII string to the UART.
65 * _mips_cps_putx4 - write a 4b hex value to the UART
66 * @a0: the 4b value to write to the UART
67 * @t9: UART base address
69 * Write a single hexadecimal character to the UART.
82 * _mips_cps_putx8 - write an 8b hex value to the UART
[all …]
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| /kernel/linux/linux-4.19/arch/mips/kernel/ |
| D | cps-vec-ns16550.S | 22 * _mips_cps_putc() - write a character to the UART
24 * @t9: UART base address
35 * _mips_cps_puts() - write a string to the UART
37 * @t9: UART base address
39 * Write a null-terminated ASCII string to the UART.
55 * _mips_cps_putx4 - write a 4b hex value to the UART
56 * @a0: the 4b value to write to the UART
57 * @t9: UART base address
59 * Write a single hexadecimal character to the UART.
72 * _mips_cps_putx8 - write an 8b hex value to the UART
[all …]
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| /kernel/linux/linux-5.10/arch/arm/include/debug/ |
| D | tegra.S | 45 #define checkuart(rp, rv, lhu, bit, uart) \ argument
50 /* Test UART's reset bit */ \
52 /* If set, can't use UART; jump to save no UART */ \
58 /* Test UART's clock enable bit */ \
60 /* If clear, can't use UART; jump to save no UART */ \
62 /* Passed all tests, load address of UART registers */ \
63 ldr rp, =TEGRA_UART##uart##_BASE ; \
64 /* Jump to save UART address */ \
85 cmp \rv, #2 @ 2 and 3 mean DCC, UART
89 11: lsr \rv, \rp, #15 @ 17:15 are UART ID
[all …]
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| /kernel/linux/linux-5.10/include/uapi/linux/ |
| D | serial_core.h | 31 #define PORT_RM9000 16 /* PMC-Sierra RM9xxx internal UART */
32 #define PORT_OCTEON 17 /* Cavium OCTEON internal UART */
33 #define PORT_AR7 18 /* Texas Instruments AR7 internal UART */
34 #define PORT_U6_16550A 19 /* ST-Ericsson U6xxx internal UART */
35 #define PORT_TEGRA 20 /* NVIDIA Tegra internal UART */
36 #define PORT_XR17D15X 21 /* Exar XR17D15x UART */
37 #define PORT_LPC3220 22 /* NXP LPC32xx SoC "Standard" UART */
41 #define PORT_ALTR_16550_F32 26 /* Altera 16550 UART with 32 FIFOs */
42 #define PORT_ALTR_16550_F64 27 /* Altera 16550 UART with 64 FIFOs */
43 #define PORT_ALTR_16550_F128 28 /* Altera 16550 UART with 128 FIFOs */
[all …]
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| /kernel/linux/linux-4.19/arch/arm/include/debug/ |
| D | tegra.S | 54 #define checkuart(rp, rv, lhu, bit, uart) \ argument
59 /* Test UART's reset bit */ \
61 /* If set, can't use UART; jump to save no UART */ \
67 /* Test UART's clock enable bit */ \
69 /* If clear, can't use UART; jump to save no UART */ \
71 /* Passed all tests, load address of UART registers */ \
72 ldr rp, =TEGRA_UART##uart##_BASE ; \
73 /* Jump to save UART address */ \
94 cmp \rv, #2 @ 2 and 3 mean DCC, UART
98 11: lsr \rv, \rp, #15 @ 17:15 are UART ID
[all …]
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