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/kernel/linux/linux-5.10/drivers/amba/
Dtegra-ahb.c21 #include <soc/tegra/ahb.h>
23 #define DRV_NAME "tegra-ahb"
79 * 0x4 for the AHB IP block. According to the TRM, the low byte
126 static inline u32 gizmo_readl(struct tegra_ahb *ahb, u32 offset) in gizmo_readl() argument
128 return readl(ahb->regs + offset); in gizmo_readl()
131 static inline void gizmo_writel(struct tegra_ahb *ahb, u32 value, u32 offset) in gizmo_writel() argument
133 writel(value, ahb->regs + offset); in gizmo_writel()
141 struct tegra_ahb *ahb; in tegra_ahb_enable_smmu() local
146 ahb = dev_get_drvdata(dev); in tegra_ahb_enable_smmu()
147 val = gizmo_readl(ahb, AHB_ARBITRATION_XBAR_CTRL); in tegra_ahb_enable_smmu()
[all …]
/kernel/linux/linux-4.19/drivers/amba/
Dtegra-ahb.c30 #include <soc/tegra/ahb.h>
32 #define DRV_NAME "tegra-ahb"
88 * 0x4 for the AHB IP block. According to the TRM, the low byte
135 static inline u32 gizmo_readl(struct tegra_ahb *ahb, u32 offset) in gizmo_readl() argument
137 return readl(ahb->regs + offset); in gizmo_readl()
140 static inline void gizmo_writel(struct tegra_ahb *ahb, u32 value, u32 offset) in gizmo_writel() argument
142 writel(value, ahb->regs + offset); in gizmo_writel()
148 struct tegra_ahb *ahb = dev_get_drvdata(dev); in tegra_ahb_match_by_smmu() local
151 return (ahb->dev->of_node == dn) ? 1 : 0; in tegra_ahb_match_by_smmu()
158 struct tegra_ahb *ahb; in tegra_ahb_enable_smmu() local
[all …]
/kernel/linux/linux-4.19/arch/unicore32/include/mach/
DPKUnity.h31 * 0x90000000 - 0x97FFFFFF 128MB PCI AHB-PCI MEM-mapping
32 * 0x98000000 - 0x9FFFFFFF 128MB PCI PCI-AHB MEM-mapping
44 * PKUNITY System Bus Addresses (AHB): 0xC0000000 - 0xEDFFFFFF (640MB)
48 /* AHB-0 is DDR2 SDRAM */
49 /* AHB-1 is PCI Space */
50 #define PKUNITY_ARBITER_BASE (PKUNITY_AHB_BASE + 0x000000) /* AHB-2 */
51 #define PKUNITY_DDR2CTRL_BASE (PKUNITY_AHB_BASE + 0x100000) /* AHB-3 */
52 #define PKUNITY_DMAC_BASE (PKUNITY_AHB_BASE + 0x200000) /* AHB-4 */
54 #define PKUNITY_UMAL_BASE (PKUNITY_AHB_BASE + 0x300000) /* AHB-5 */
56 #define PKUNITY_USB_BASE (PKUNITY_AHB_BASE + 0x400000) /* AHB-6 */
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra20-ahb.txt1 NVIDIA Tegra AHB
4 - compatible : For Tegra20, must contain "nvidia,tegra20-ahb". For
5 Tegra30, must contain "nvidia,tegra30-ahb". Otherwise, must contain
6 '"nvidia,<chip>-ahb", "nvidia,tegra30-ahb"' where <chip> is tegra124,
14 ahb: ahb@6000c004 {
15 compatible = "nvidia,tegra20-ahb";
16 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra20-ahb.txt1 NVIDIA Tegra AHB
4 - compatible : For Tegra20, must contain "nvidia,tegra20-ahb". For
5 Tegra30, must contain "nvidia,tegra30-ahb". Otherwise, must contain
6 '"nvidia,<chip>-ahb", "nvidia,tegra30-ahb"' where <chip> is tegra124,
14 ahb: ahb@6000c004 {
15 compatible = "nvidia,tegra20-ahb";
16 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
/kernel/linux/linux-4.19/drivers/clk/imx/
Dclk-imx35.c38 unsigned char arm, ahb, sel; member
42 { .arm = 1, .ahb = 4, .sel = 0},
43 { .arm = 1, .ahb = 3, .sel = 1},
44 { .arm = 2, .ahb = 2, .sel = 0},
45 { .arm = 0, .ahb = 0, .sel = 0},
46 { .arm = 0, .ahb = 0, .sel = 0},
47 { .arm = 0, .ahb = 0, .sel = 0},
48 { .arm = 4, .ahb = 1, .sel = 0},
49 { .arm = 1, .ahb = 5, .sel = 0},
50 { .arm = 1, .ahb = 8, .sel = 0},
[all …]
Dclk-imx27.c40 "ahb", "ipg", "per1_div", "per2_div",
80 clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2); in _mx27_clocks_init()
81 clk[IMX27_CLK_IPG] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); in _mx27_clocks_init()
83 clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4); in _mx27_clocks_init()
84 clk[IMX27_CLK_IPG] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1); in _mx27_clocks_init()
87 clk[IMX27_CLK_MSHC_DIV] = imx_clk_divider("mshc_div", "ahb", CCM_PCDR0, 0, 6); in _mx27_clocks_init()
88 clk[IMX27_CLK_NFC_DIV] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4); in _mx27_clocks_init()
150 clk[IMX27_CLK_USB_AHB_GATE] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11); in _mx27_clocks_init()
151 clk[IMX27_CLK_SLCDC_AHB_GATE] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12); in _mx27_clocks_init()
152 clk[IMX27_CLK_SAHARA_AHB_GATE] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13); in _mx27_clocks_init()
[all …]
Dclk-imx25.c59 static const char *per_sel_clks[] = { "ahb", "upll", };
60 static const char *cko_sel_clks[] = { "dummy", "osc", "cpu", "ahb",
66 dummy, osc, mpll, upll, mpll_cpu_3_4, cpu_sel, cpu, ahb, usb_div, ipg, enumerator
109 clk[ahb] = imx_clk_divider("ahb", "cpu", ccm(CCM_CCTL), 28, 2); in __mx25_clocks_init()
111 clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); in __mx25_clocks_init()
163 clk[ata_ahb] = imx_clk_gate("ata_ahb", "ahb", ccm(CCM_CGCR0), 16); in __mx25_clocks_init()
165 clk[csi_ahb] = imx_clk_gate("csi_ahb", "ahb", ccm(CCM_CGCR0), 18); in __mx25_clocks_init()
166 clk[emi_ahb] = imx_clk_gate("emi_ahb", "ahb", ccm(CCM_CGCR0), 19); in __mx25_clocks_init()
167 clk[esai_ahb] = imx_clk_gate("esai_ahb", "ahb", ccm(CCM_CGCR0), 20); in __mx25_clocks_init()
168 clk[esdhc1_ahb] = imx_clk_gate("esdhc1_ahb", "ahb", ccm(CCM_CGCR0), 21); in __mx25_clocks_init()
[all …]
/kernel/linux/linux-5.10/drivers/clk/imx/
Dclk-imx35.c34 unsigned char arm, ahb, sel; member
38 { .arm = 1, .ahb = 4, .sel = 0},
39 { .arm = 1, .ahb = 3, .sel = 1},
40 { .arm = 2, .ahb = 2, .sel = 0},
41 { .arm = 0, .ahb = 0, .sel = 0},
42 { .arm = 0, .ahb = 0, .sel = 0},
43 { .arm = 0, .ahb = 0, .sel = 0},
44 { .arm = 4, .ahb = 1, .sel = 0},
45 { .arm = 1, .ahb = 5, .sel = 0},
46 { .arm = 1, .ahb = 8, .sel = 0},
[all …]
Dclk-imx27.c41 "ahb", "ipg", "per1_div", "per2_div",
70 clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2); in _mx27_clocks_init()
71 clk[IMX27_CLK_IPG] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); in _mx27_clocks_init()
73 clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4); in _mx27_clocks_init()
74 clk[IMX27_CLK_IPG] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1); in _mx27_clocks_init()
77 clk[IMX27_CLK_MSHC_DIV] = imx_clk_divider("mshc_div", "ahb", CCM_PCDR0, 0, 6); in _mx27_clocks_init()
78 clk[IMX27_CLK_NFC_DIV] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4); in _mx27_clocks_init()
140 clk[IMX27_CLK_USB_AHB_GATE] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11); in _mx27_clocks_init()
141 clk[IMX27_CLK_SLCDC_AHB_GATE] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12); in _mx27_clocks_init()
142 clk[IMX27_CLK_SAHARA_AHB_GATE] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13); in _mx27_clocks_init()
[all …]
Dclk-imx25.c46 static const char *per_sel_clks[] = { "ahb", "upll", };
47 static const char *cko_sel_clks[] = { "dummy", "osc", "cpu", "ahb",
53 dummy, osc, mpll, upll, mpll_cpu_3_4, cpu_sel, cpu, ahb, usb_div, ipg, enumerator
86 clk[ahb] = imx_clk_divider("ahb", "cpu", ccm(CCM_CCTL), 28, 2); in __mx25_clocks_init()
88 clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); in __mx25_clocks_init()
140 clk[ata_ahb] = imx_clk_gate("ata_ahb", "ahb", ccm(CCM_CGCR0), 16); in __mx25_clocks_init()
142 clk[csi_ahb] = imx_clk_gate("csi_ahb", "ahb", ccm(CCM_CGCR0), 18); in __mx25_clocks_init()
143 clk[emi_ahb] = imx_clk_gate("emi_ahb", "ahb", ccm(CCM_CGCR0), 19); in __mx25_clocks_init()
144 clk[esai_ahb] = imx_clk_gate("esai_ahb", "ahb", ccm(CCM_CGCR0), 20); in __mx25_clocks_init()
145 clk[esdhc1_ahb] = imx_clk_gate("esdhc1_ahb", "ahb", ccm(CCM_CGCR0), 21); in __mx25_clocks_init()
[all …]
/kernel/linux/linux-4.19/drivers/clk/sunxi-ng/
Dccu-sun4i-a10.c250 .hw.init = CLK_HW_INIT("ahb", "axi", &ccu_div_ops, 0),
271 .hw.init = CLK_HW_INIT_PARENTS("ahb",
285 static SUNXI_CCU_DIV_TABLE(apb0_clk, "apb0", "ahb",
296 static SUNXI_CCU_GATE(axi_dram_clk, "axi-dram", "ahb",
299 static SUNXI_CCU_GATE(ahb_otg_clk, "ahb-otg", "ahb",
301 static SUNXI_CCU_GATE(ahb_ehci0_clk, "ahb-ehci0", "ahb",
303 static SUNXI_CCU_GATE(ahb_ohci0_clk, "ahb-ohci0", "ahb",
305 static SUNXI_CCU_GATE(ahb_ehci1_clk, "ahb-ehci1", "ahb",
307 static SUNXI_CCU_GATE(ahb_ohci1_clk, "ahb-ohci1", "ahb",
309 static SUNXI_CCU_GATE(ahb_ss_clk, "ahb-ss", "ahb",
[all …]
Dccu-sun5i.c221 .hw.init = CLK_HW_INIT_PARENTS("ahb",
235 static SUNXI_CCU_DIV_TABLE(apb0_clk, "apb0", "ahb",
248 static SUNXI_CCU_GATE(ahb_otg_clk, "ahb-otg", "ahb",
250 static SUNXI_CCU_GATE(ahb_ehci_clk, "ahb-ehci", "ahb",
252 static SUNXI_CCU_GATE(ahb_ohci_clk, "ahb-ohci", "ahb",
254 static SUNXI_CCU_GATE(ahb_ss_clk, "ahb-ss", "ahb",
256 static SUNXI_CCU_GATE(ahb_dma_clk, "ahb-dma", "ahb",
258 static SUNXI_CCU_GATE(ahb_bist_clk, "ahb-bist", "ahb",
260 static SUNXI_CCU_GATE(ahb_mmc0_clk, "ahb-mmc0", "ahb",
262 static SUNXI_CCU_GATE(ahb_mmc1_clk, "ahb-mmc1", "ahb",
[all …]
/kernel/linux/linux-5.10/drivers/clk/sunxi-ng/
Dccu-sun4i-a10.c244 .hw.init = CLK_HW_INIT("ahb", "axi", &ccu_div_ops, 0),
265 .hw.init = CLK_HW_INIT_PARENTS("ahb",
279 static SUNXI_CCU_DIV_TABLE(apb0_clk, "apb0", "ahb",
290 static SUNXI_CCU_GATE(axi_dram_clk, "axi-dram", "ahb",
293 static SUNXI_CCU_GATE(ahb_otg_clk, "ahb-otg", "ahb",
295 static SUNXI_CCU_GATE(ahb_ehci0_clk, "ahb-ehci0", "ahb",
297 static SUNXI_CCU_GATE(ahb_ohci0_clk, "ahb-ohci0", "ahb",
299 static SUNXI_CCU_GATE(ahb_ehci1_clk, "ahb-ehci1", "ahb",
301 static SUNXI_CCU_GATE(ahb_ohci1_clk, "ahb-ohci1", "ahb",
303 static SUNXI_CCU_GATE(ahb_ss_clk, "ahb-ss", "ahb",
[all …]
Dccu-sun5i.c214 .hw.init = CLK_HW_INIT_PARENTS("ahb",
228 static SUNXI_CCU_DIV_TABLE(apb0_clk, "apb0", "ahb",
241 static SUNXI_CCU_GATE(ahb_otg_clk, "ahb-otg", "ahb",
243 static SUNXI_CCU_GATE(ahb_ehci_clk, "ahb-ehci", "ahb",
245 static SUNXI_CCU_GATE(ahb_ohci_clk, "ahb-ohci", "ahb",
247 static SUNXI_CCU_GATE(ahb_ss_clk, "ahb-ss", "ahb",
249 static SUNXI_CCU_GATE(ahb_dma_clk, "ahb-dma", "ahb",
251 static SUNXI_CCU_GATE(ahb_bist_clk, "ahb-bist", "ahb",
253 static SUNXI_CCU_GATE(ahb_mmc0_clk, "ahb-mmc0", "ahb",
255 static SUNXI_CCU_GATE(ahb_mmc1_clk, "ahb-mmc1", "ahb",
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dallwinner,sun5i-a13-ahb-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun5i-a13-ahb-clk.yaml#
7 title: Allwinner A13 AHB Clock Device Tree Bindings
20 const: allwinner,sun5i-a13-ahb-clk
44 ahb@1c20054 {
46 compatible = "allwinner,sun5i-a13-ahb-clk";
49 clock-output-names = "ahb";
Dallwinner,sun4i-a10-ahb-clk.yaml4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ahb-clk.yaml#
7 title: Allwinner A10 AHB Clock Device Tree Bindings
21 - allwinner,sun4i-a10-ahb-clk
51 const: allwinner,sun4i-a10-ahb-clk
82 ahb@1c20054 {
84 compatible = "allwinner,sun4i-a10-ahb-clk";
87 clock-output-names = "ahb";
Dnspire-clock.txt5 "lsi,nspire-cx-ahb-divider" for the AHB divider in the CX model
6 "lsi,nspire-classic-ahb-divider" for the AHB divider in the older model
14 - clocks: For the "nspire-*-ahb-divider" compatible clocks, this is the parent
/kernel/linux/linux-4.19/drivers/clk/
Dclk-gemini.c93 { 2, "gmac0-gate", "ahb", 0 },
94 { 3, "gmac1-gate", "ahb", 0 },
95 { 4, "sata0-gate", "ahb", 0 },
96 { 5, "sata1-gate", "ahb", 0 },
97 { 6, "usb0-gate", "ahb", 0 },
98 { 7, "usb1-gate", "ahb", 0 },
99 { 8, "ide-gate", "ahb", 0 },
100 { 9, "pci-gate", "ahb", 0 },
105 { 10, "ddr-gate", "ahb", CLK_IS_CRITICAL },
110 { 11, "flash-gate", "ahb", CLK_IGNORE_UNUSED },
[all …]
/kernel/linux/linux-5.10/drivers/clk/
Dclk-gemini.c93 { 2, "gmac0-gate", "ahb", 0 },
94 { 3, "gmac1-gate", "ahb", 0 },
95 { 4, "sata0-gate", "ahb", 0 },
96 { 5, "sata1-gate", "ahb", 0 },
97 { 6, "usb0-gate", "ahb", 0 },
98 { 7, "usb1-gate", "ahb", 0 },
99 { 8, "ide-gate", "ahb", 0 },
100 { 9, "pci-gate", "ahb", 0 },
105 { 10, "ddr-gate", "ahb", CLK_IS_CRITICAL },
110 { 11, "flash-gate", "ahb", CLK_IGNORE_UNUSED },
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/clock/
Dsunxi.txt24 "allwinner,sun4i-a10-ahb-clk" - for the AHB clock
25 "allwinner,sun5i-a13-ahb-clk" - for the AHB clock on A13
26 "allwinner,sun9i-a80-ahb-clk" - for the AHB bus clocks on A80
27 "allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10
28 "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
29 "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
30 "allwinner,sun7i-a20-ahb-gates-clk" - for the AHB gates on A20
218 clock-names = "ahb";
220 reset-names = "ahb";
Dnspire-clock.txt5 "lsi,nspire-cx-ahb-divider" for the AHB divider in the CX model
6 "lsi,nspire-classic-ahb-divider" for the AHB divider in the older model
14 - clocks: For the "nspire-*-ahb-divider" compatible clocks, this is the parent
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/crypto/
Dsun4i-ss.txt7 - clocks : List of clock specifiers, corresponding to ahb and ss.
9 * "ahb" : AHB gating clock
14 - reset-names : must contain "ahb"
22 clock-names = "ahb", "mod";
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/
Dqcom,pcie.txt86 - "iface" Configuration AHB clock
121 - "ahb" AHB clock
128 - "iface" AHB clock
156 - "ahb" AHB reset
181 - "ahb" AHB reset
182 - "phy_ahb" PHY AHB reset
194 - "ahb" AHB Reset
206 - "ahb" AHB reset
294 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
/kernel/linux/linux-5.10/drivers/clk/sprd/
Dsc9860-clk.c524 static SPRD_COMP_CLK(sp_ahb, "sp-ahb", sp_ahb_parents, 0x2d0,
1339 static SPRD_MUX_CLK(ahb_vsp, "ahb-vsp", ahb_parents, 0x20,
1385 static SPRD_SC_GATE_CLK(vsp_dec_eb, "vsp-dec-eb", "ahb-vsp", 0x0,
1387 static SPRD_SC_GATE_CLK(vsp_ckg_eb, "vsp-ckg-eb", "ahb-vsp", 0x0,
1389 static SPRD_SC_GATE_CLK(vsp_mmu_eb, "vsp-mmu-eb", "ahb-vsp", 0x0,
1391 static SPRD_SC_GATE_CLK(vsp_enc_eb, "vsp-enc-eb", "ahb-vsp", 0x0,
1393 static SPRD_SC_GATE_CLK(vpp_eb, "vpp-eb", "ahb-vsp", 0x0,
1395 static SPRD_SC_GATE_CLK(vsp_26m_eb, "vsp-26m-eb", "ahb-vsp", 0x0,
1397 static SPRD_GATE_CLK(vsp_axi_gate, "vsp-axi-gate", "ahb-vsp", 0x8,
1399 static SPRD_GATE_CLK(vsp_enc_gate, "vsp-enc-gate", "ahb-vsp", 0x8,
[all …]

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