Searched full:architecturally (Results 1 – 25 of 119) sorted by relevance
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| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/arm64/arm/cortex-a76-n1/ |
| D | instruction.json | 3 …"PublicDescription": "Software increment. Instruction architecturally executed (condition code che…
9 …"PublicDescription": "Instruction architecturally executed. This event counts all retired instruct…
12 "BriefDescription": "Instruction architecturally executed."
17 …"BriefDescription": "Instruction architecturally executed, condition code check pass, exception re…
20 …"PublicDescription": "Instruction architecturally executed, condition code check pass, write to CO…
23 …"BriefDescription": "Instruction architecturally executed, condition code check pass, write to CON…
31 …"PublicDescription": "Instruction architecturally executed, condition code check pass, write to TT…
34 …"BriefDescription": "Instruction architecturally executed, condition code check pass, write to TTB…
37 …"PublicDescription": "Instruction architecturally executed, branch. This event counts all branches…
40 "BriefDescription": "Instruction architecturally executed, branch."
[all …]
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| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/arm64/ampere/emag/ |
| D | instruction.json | 42 "PublicDescription": "Instruction architecturally executed, software increment",
48 "PublicDescription": "Instruction architecturally executed",
54 …"PublicDescription": "Instruction architecturally executed, condition code check pass, write to CO…
66 … "PublicDescription": "Instruction architecturally executed (condition check pass), write to TTBR",
72 …"PublicDescription": "Instruction architecturally executed, branch. This event counts all branches…
78 …"PublicDescription": "Instruction architecturally executed, mispredicted branch. This event counts…
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| D | exception.json | 45 …"PublicDescription": "Instruction architecturally executed, condition check pass, exception return…
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| /kernel/linux/linux-5.10/drivers/soc/qcom/ |
| D | kryo-l2-accessors.c | 21 * Use architecturally required barriers for ordering between system register
41 * Use architecturally required barriers for ordering between system register
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| /kernel/linux/linux-5.10/Documentation/arm64/ |
| D | amu.rst | 27 of four fixed and architecturally defined 64-bit event counters.
32 - Instructions retired: increments with every architecturally executed
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| /kernel/linux/linux-5.10/arch/arm/include/asm/ |
| D | virt.h | 14 * architecturally defined flag bit here.
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| /kernel/linux/linux-4.19/tools/arch/ia64/include/asm/ |
| D | barrier.h | 22 * architecturally visible effects of a memory access have occurred
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| /kernel/linux/linux-5.10/tools/arch/ia64/include/asm/ |
| D | barrier.h | 22 * architecturally visible effects of a memory access have occurred
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| /kernel/linux/linux-5.10/arch/x86/include/asm/ |
| D | spec-ctrl.h | 11 * would be easier if SPEC_CTRL were architecturally maskable or
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| D | debugreg.h | 103 dr7 &= ~0x400; /* architecturally set bit */ in local_db_save()
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| /kernel/linux/linux-4.19/arch/x86/include/asm/ |
| D | spec-ctrl.h | 11 * would be easier if SPEC_CTRL were architecturally maskable or
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/interrupt-controller/ |
| D | riscv,cpu-intc.txt | 13 timer interrupt comes from an architecturally mandated real-time timer that is
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/ |
| D | riscv,cpu-intc.txt | 13 timer interrupt comes from an architecturally mandated real-time timer that is
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| /kernel/linux/linux-4.19/arch/arm/kvm/ |
| D | trace.h | 10 /* Architecturally implementation defined CP15 register access */
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| D | reset.c | 51 * virtual CPU struct to their architecturally defined reset values.
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| /kernel/linux/linux-5.10/arch/ia64/include/asm/ |
| D | barrier.h | 20 * architecturally visible effects of a memory access have occurred
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| /kernel/linux/linux-4.19/arch/arm/include/asm/ |
| D | virt.h | 27 * architecturally defined flag bit here.
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| /kernel/linux/linux-4.19/arch/ia64/include/asm/ |
| D | barrier.h | 20 * architecturally visible effects of a memory access have occurred
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/ |
| D | coresight-cti.yaml | 37 architecturally connected CTI an additional compatible string is used to
235 # v8 architecturally defined CTI - CPU + ETM connections generated by the
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| /kernel/linux/linux-4.19/Documentation/virtual/kvm/devices/ |
| D | arm-vgic-v3.txt | 89 architecturally defined behavior to allow software a full view of the
111 The GICD_STATUSR and GICR_STATUSR registers are architecturally defined such
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/ |
| D | arm,arch_timer_mmio.yaml | 51 registers, which contain their architecturally-defined reset values. Only
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| D | arm,arch_timer.yaml | 77 registers, which contain their architecturally-defined reset values. Only
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/timer/ |
| D | arm,arch_timer.txt | 44 architecturally-defined reset values. Only supported for 32-bit
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/ |
| D | nvidia,tegra30-mc.yaml | 15 Tegra30 Memory Controller architecturally consists of the following parts:
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| /kernel/linux/linux-5.10/arch/x86/lib/ |
| D | retpoline.S | 109 * We subsequently jump backwards and architecturally execute the RET.
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