| /kernel/linux/linux-5.10/drivers/pinctrl/samsung/ |
| D | pinctrl-samsung.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
25 * enum pincfg_type - possible pin configuration types supported.
46 * packed together into a 16-bits. The upper 8-bits represent the configuration
47 * type and the lower 8-bits hold the value of the configuration type.
57 * enum eint_type - possible external interrupt types.
58 * @EINT_TYPE_NONE: bank does not support external interrupts
59 * @EINT_TYPE_GPIO: bank supportes external gpio interrupts
60 * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts
61 * @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts
[all …]
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| /kernel/linux/linux-4.19/drivers/pinctrl/samsung/ |
| D | pinctrl-samsung.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
25 * enum pincfg_type - possible pin configuration types supported.
46 * packed together into a 16-bits. The upper 8-bits represent the configuration
47 * type and the lower 8-bits hold the value of the configuration type.
57 * enum eint_type - possible external interrupt types.
58 * @EINT_TYPE_NONE: bank does not support external interrupts
59 * @EINT_TYPE_GPIO: bank supportes external gpio interrupts
60 * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts
61 * @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pinctrl/ |
| D | pinctrl-st.txt | 3 Each multi-function pin is controlled, driven and routed through the
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
14 GPIO bank can have one of the two possible types of interrupt-wirings.
17 reduces number of overall interrupts numbers required. All these banks belong to
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
23 | |----> [gpio-bank (... )]
24 |_________|----> [gpio-bank (n + 7)]
26 Second type has a dedicated interrupt per gpio bank.
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/pinctrl/ |
| D | pinctrl-st.txt | 3 Each multi-function pin is controlled, driven and routed through the
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
14 GPIO bank can have one of the two possible types of interrupt-wirings.
17 reduces number of overall interrupts numbers required. All these banks belong to
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
23 | |----> [gpio-bank (... )]
24 |_________|----> [gpio-bank (n + 7)]
26 Second type has a dedicated interrupt per gpio bank.
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpio/ |
| D | gpio-zynq.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
20 #define DRIVER_NAME "zynq-gpio"
46 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
49 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
52 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
55 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
58 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
61 ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
64 /* LSW Mask & Data -WO */
[all …]
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| /kernel/linux/linux-4.19/drivers/gpio/ |
| D | gpio-zynq.c | 4 * Copyright (C) 2009 - 2014 Xilinx, Inc.
23 #define DRIVER_NAME "zynq-gpio"
46 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
49 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
52 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
55 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
58 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
61 ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
64 /* LSW Mask & Data -WO */
65 #define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK)) argument
[all …]
|
| /kernel/linux/linux-5.10/drivers/dma/ipu/ |
| D | ipu_irq.c | 1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/dma/ipu-dma.h>
20 * Register read / write - shall be inlined by the compiler
24 return __raw_readl(ipu->reg_ipu + reg); in ipu_read_reg()
29 __raw_writel(value, ipu->reg_ipu + reg); in ipu_write_reg()
72 struct ipu_irq_bank *bank; member
96 struct ipu_irq_bank *bank; in ipu_irq_unmask() local
102 bank = map->bank; in ipu_irq_unmask()
103 if (!bank) { in ipu_irq_unmask()
105 pr_err("IPU: %s(%u) - unmapped!\n", __func__, d->irq); in ipu_irq_unmask()
[all …]
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| /kernel/linux/linux-4.19/drivers/dma/ipu/ |
| D | ipu_irq.c | 18 #include <linux/dma/ipu-dma.h>
23 * Register read / write - shall be inlined by the compiler
27 return __raw_readl(ipu->reg_ipu + reg); in ipu_read_reg()
32 __raw_writel(value, ipu->reg_ipu + reg); in ipu_write_reg()
75 struct ipu_irq_bank *bank; member
99 struct ipu_irq_bank *bank; in ipu_irq_unmask() local
105 bank = map->bank; in ipu_irq_unmask()
106 if (!bank) { in ipu_irq_unmask()
108 pr_err("IPU: %s(%u) - unmapped!\n", __func__, d->irq); in ipu_irq_unmask()
112 reg = ipu_read_reg(bank->ipu, bank->control); in ipu_irq_unmask()
[all …]
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| /kernel/linux/linux-5.10/drivers/pinctrl/ |
| D | pinctrl-equilibrium.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
18 #define DRV_CUR_PINS 16 /* Drive Current pin number per register */
74 * @nr_groups: number of groups included in @groups.
83 * struct eqbr_pin_bank: represent a pin bank.
84 * @membase: base address of the pin bank register.
85 * @id: bank id, to idenify the unique bank.
86 * @pin_base: starting pin number of the pin bank.
87 * @nr_pins: number of the pins of the pin bank.
88 * @aval_pinmap: available pin bitmap of the pin bank.
101 * @bank: pointer to corresponding pin bank.
[all …]
|
| /kernel/linux/linux-4.19/Documentation/hwmon/ |
| D | abituguru-datasheet | 13 Olle Sandberg <ollebull@gmail.com>, 2005-05-25
26 Hans de Goede <j.w.r.degoede@hhs.nl>, 28-01-2006
32 As far as known the uGuru is always placed at and using the (ISA) I/O-ports
33 0xE0 and 0xE4, so we don't have to scan any port-range, just check what the two
34 ports are holding for detection. We will refer to 0xE0 as CMD (command-port)
38 present. We have to check for two different values at data-port, because
40 later on attached again data-port will hold 0x08, more about this later.
56 ----------
58 The uGuru has a number of different addressing levels. The first addressing
59 level we will call banks. A bank holds data for one or more sensors. The data
[all …]
|
| /kernel/linux/linux-5.10/drivers/thermal/ |
| D | mtk_thermal.c | 1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/nvmem-consumer.h>
101 /* The total number of temperature sensors in the MT8173 */
104 /* The number of banks in the MT8173 */
107 /* The number of sensing points per bank */
110 /* The number of controller in the MT8173 */
174 /* The total number of temperature sensors in the MT2701 */
177 /* The number of sensing points per bank */
180 /* The number of controller in the MT2701 */
195 /* The total number of temperature sensors in the MT2712 */
[all …]
|
| /kernel/linux/linux-4.19/include/linux/soundwire/ |
| D | sdw.h | 1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
2 // Copyright(c) 2015-17 Intel Corporation.
12 /* SDW Broadcast Device Number */
15 /* SDW Enumeration Device Number */
22 /* SDW Master Device Number, not supported yet */
45 * enum sdw_slave_status - Slave status
59 * enum sdw_command_response - Command response as defined by SDW spec
111 * enum sdw_p15_behave - Slave Port 15 behaviour when the Master attempts a
122 * enum sdw_dpn_type - Data port types
137 * enum sdw_clk_stop_mode - Clock Stop modes
[all …]
|
| /kernel/linux/linux-5.10/Documentation/hwmon/ |
| D | abituguru-datasheet.rst | 14 Olle Sandberg <ollebull@gmail.com>, 2005-05-25
27 Hans de Goede <j.w.r.degoede@hhs.nl>, 28-01-2006
33 As far as known the uGuru is always placed at and using the (ISA) I/O-ports
34 0xE0 and 0xE4, so we don't have to scan any port-range, just check what the two
35 ports are holding for detection. We will refer to 0xE0 as CMD (command-port)
39 present. We have to check for two different values at data-port, because
41 later on attached again data-port will hold 0x08, more about this later.
57 ----------
59 The uGuru has a number of different addressing levels. The first addressing
60 level we will call banks. A bank holds data for one or more sensors. The data
[all …]
|
| /kernel/linux/linux-5.10/drivers/mtd/nand/raw/ |
| D | denali.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright (c) 2009 - 2010, Intel Corporation and its suppliers.
18 #define DEVICE_RESET__BANK(bank) BIT(bank) argument
36 #define RB_PIN_ENABLED__BANK(bank) BIT(bank) argument
208 #define INTR_STATUS(bank) (0x410 + (bank) * 0x50) argument
209 #define INTR_EN(bank) (0x420 + (bank) * 0x50) argument
230 #define PAGE_CNT(bank) (0x430 + (bank) * 0x50) argument
231 #define ERR_PAGE_ADDR(bank) (0x440 + (bank) * 0x50) argument
232 #define ERR_BLOCK_ADDR(bank) (0x450 + (bank) * 0x50) argument
254 #define ECC_COR_INFO(bank) (0x650 + (bank) / 2 * 0x10) argument
[all …]
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| /kernel/linux/linux-4.19/drivers/thermal/ |
| D | mtk_thermal.c | 23 #include <linux/nvmem-consumer.h>
99 /* The total number of temperature sensors in the MT8173 */
102 /* The number of banks in the MT8173 */
105 /* The number of sensing points per bank */
135 /* The total number of temperature sensors in the MT2701 */
138 /* The number of sensing points per bank */
150 /* The total number of temperature sensors in the MT2712 */
153 /* The number of sensing points per bank */
258 * The MT8173 thermal controller has four banks. Each bank can read up to
260 * temperature sensors. We use each bank to measure a certain area of the
[all …]
|
| /kernel/linux/linux-4.19/drivers/memory/ |
| D | jz4780-nemc.c | 5 * Author: Alex Smith <alex@alex-smith.me.uk>
23 #include <linux/jz4780-nemc.h>
25 #define NEMC_SMCRn(n) (0x14 + (((n) - 1) * 4))
43 #define NEMC_NFCSR_NFEn(n) BIT(((n) - 1) << 1)
44 #define NEMC_NFCSR_NFCEn(n) BIT((((n) - 1) << 1) + 1)
45 #define NEMC_NFCSR_TNFEn(n) BIT(16 + (n) - 1)
57 * jz4780_nemc_num_banks() - count the number of banks referenced by a device
60 * Return: The number of unique NEMC banks referred to by the specified NEMC
61 * child device. Unique here means that a device that references the same bank
67 unsigned int bank, count = 0; in jz4780_nemc_num_banks() local
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/soc/fsl/cpm_qe/ |
| D | gpio.txt | 1 Every GPIO controller node must have #gpio-cells property defined,
2 this information will be used to translate gpio-specifiers.
10 - compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b",
11 "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d",
12 "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank"
13 - #gpio-cells : Should be two. The first cell is the pin number and the
15 - gpio-controller : Marks the port as GPIO controller.
17 - fsl,cpm1-gpio-irq-mask : For banks having interrupt capability (like port C
20 - interrupts : This property provides the list of interrupt for each GPIO having
21 one as described by the fsl,cpm1-gpio-irq-mask property. There should be as
[all …]
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/soc/fsl/cpm_qe/ |
| D | gpio.txt | 1 Every GPIO controller node must have #gpio-cells property defined,
2 this information will be used to translate gpio-specifiers.
10 - compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b",
11 "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d",
12 "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank"
13 - #gpio-cells : Should be two. The first cell is the pin number and the
15 - gpio-controller : Marks the port as GPIO controller.
17 - fsl,cpm1-gpio-irq-mask : For banks having interrupt capability (like port C
20 - interrupts : This property provides the list of interrupt for each GPIO having
21 one as described by the fsl,cpm1-gpio-irq-mask property. There should be as
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/ |
| D | fsmc-nand.txt | 5 - compatible : "st,spear600-fsmc-nand", "stericsson,fsmc-nand"
6 - reg : Address range of the mtd chip
7 - reg-names: Should contain the reg names "fsmc_regs", "nand_data", "nand_addr" and "nand_cmd"
10 - bank-width : Width (in bytes) of the device. If not present, the width
12 - nand-skip-bbtscan: Indicates the BBT scanning should be skipped
13 - timings: array of 6 bytes for NAND timings. The meanings of these bytes
15 byte 0 TCLR : CLE to RE delay in number of AHB clock cycles, only 4 bits
19 byte 2 THIZ : number of HCLK clock cycles during which the data bus is
20 kept in Hi-Z (tristate) after the start of a write access.
23 byte 3 THOLD : number of HCLK clock cycles to hold the address (and data
[all …]
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/mtd/ |
| D | fsmc-nand.txt | 5 - compatible : "st,spear600-fsmc-nand", "stericsson,fsmc-nand"
6 - reg : Address range of the mtd chip
7 - reg-names: Should contain the reg names "fsmc_regs", "nand_data", "nand_addr" and "nand_cmd"
10 - bank-width : Width (in bytes) of the device. If not present, the width
12 - nand-skip-bbtscan: Indicates the BBT scanning should be skipped
13 - timings: array of 6 bytes for NAND timings. The meanings of these bytes
15 byte 0 TCLR : CLE to RE delay in number of AHB clock cycles, only 4 bits
19 byte 2 THIZ : number of HCLK clock cycles during which the data bus is
20 kept in Hi-Z (tristate) after the start of a write access.
23 byte 3 THOLD : number of HCLK clock cycles to hold the address (and data
[all …]
|
| /kernel/linux/linux-4.19/drivers/mtd/devices/ |
| D | spear_smi.c | 157 * struct spear_smi - Structure for SMI Device
165 * @cmd_complete: queue to wait for command completion of NOR-flash.
166 * @num_flashes: number of flashes actually present on board.
167 * @flash: separate structure for each Serial NOR-flash attached to SMI.
182 * struct spear_snor_flash - Structure for Serial NOR Flash
184 * @bank: Bank number(0, 1, 2, 3) for each NOR-flash.
185 * @dev_id: Device ID of NOR-flash.
187 * @mtd: MTD info for each NOR-flash.
188 * @num_parts: Total number of partition in each bank of NOR-flash.
189 * @parts: Partition info for each bank of NOR-flash.
[all …]
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| /kernel/linux/linux-5.10/drivers/mtd/devices/ |
| D | spear_smi.c | 157 * struct spear_smi - Structure for SMI Device
165 * @cmd_complete: queue to wait for command completion of NOR-flash.
166 * @num_flashes: number of flashes actually present on board.
167 * @flash: separate structure for each Serial NOR-flash attached to SMI.
182 * struct spear_snor_flash - Structure for Serial NOR Flash
184 * @bank: Bank number(0, 1, 2, 3) for each NOR-flash.
185 * @dev_id: Device ID of NOR-flash.
187 * @mtd: MTD info for each NOR-flash.
188 * @num_parts: Total number of partition in each bank of NOR-flash.
189 * @parts: Partition info for each bank of NOR-flash.
[all …]
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/memory-controllers/ |
| D | exynos-srom.txt | 4 - compatible : Should contain "samsung,exynos4210-srom".
6 - reg: offset and length of the register set
12 - #address-cells: Must be set to 2 to allow device address translation.
13 Address is specified as (bank#, offset).
15 - #size-cells: Must be set to 1 to allow device size passing
17 - ranges: Must be set up to reflect the memory layout with four integer values
18 per bank:
19 <bank-number> 0 <parent address of bank> <size>
21 Sub-nodes:
24 properties, describing configuration of the relevant SROM bank:
[all …]
|
| /kernel/linux/linux-4.19/drivers/hwspinlock/ |
| D | omap_hwspinlock.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2010-2015 Texas Instruments Incorporated - http://www.ti.com
8 * Hari Kanigeri <h-kanigeri2@ti.com>
9 * Ohad Ben-Cohen <ohad@wizery.com>
39 void __iomem *lock_addr = lock->priv; in omap_hwspinlock_trylock()
47 void __iomem *lock_addr = lock->priv; in omap_hwspinlock_unlock()
60 * The number below is taken from an hardware specs example,
76 struct device_node *node = pdev->dev.of_node; in omap_hwspinlock_probe()
77 struct hwspinlock_device *bank; in omap_hwspinlock_probe() local
86 return -ENODEV; in omap_hwspinlock_probe()
[all …]
|
| /kernel/linux/linux-5.10/drivers/memory/ |
| D | jz4780-nemc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * Author: Alex Smith <alex@alex-smith.me.uk>
21 #include <linux/jz4780-nemc.h>
23 #define NEMC_SMCRn(n) (0x14 + (((n) - 1) * 4))
43 #define NEMC_NFCSR_NFEn(n) BIT(((n) - 1) << 1)
44 #define NEMC_NFCSR_NFCEn(n) BIT((((n) - 1) << 1) + 1)
45 #define NEMC_NFCSR_TNFEn(n) BIT(16 + (n) - 1)
62 * jz4780_nemc_num_banks() - count the number of banks referenced by a device
65 * Return: The number of unique NEMC banks referred to by the specified NEMC
66 * child device. Unique here means that a device that references the same bank
[all …]
|