| /kernel/linux/linux-4.19/drivers/pinctrl/tegra/ |
| D | pinctrl-tegra.c | 4 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
9 * Copyright (C) 2009-2011 ST-Ericsson AB
33 #include "../pinctrl-utils.h"
34 #include "pinctrl-tegra.h"
36 static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg) in pmx_readl() argument
38 return readl(pmx->regs[bank] + reg); in pmx_readl()
41 static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg) in pmx_writel() argument
43 writel_relaxed(val, pmx->regs[bank] + reg); in pmx_writel()
45 pmx_readl(pmx, bank, reg); in pmx_writel()
52 return pmx->soc->ngroups; in tegra_pinctrl_get_groups_count()
[all …]
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| /kernel/linux/linux-5.10/drivers/pinctrl/tegra/ |
| D | pinctrl-tegra.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
10 * Copyright (C) 2009-2011 ST-Ericsson AB
25 #include "../pinctrl-utils.h"
26 #include "pinctrl-tegra.h"
28 static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg) in pmx_readl() argument
30 return readl(pmx->regs[bank] + reg); in pmx_readl()
33 static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg) in pmx_writel() argument
35 writel_relaxed(val, pmx->regs[bank] + reg); in pmx_writel()
37 pmx_readl(pmx, bank, reg); in pmx_writel()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mtd/ |
| D | mtd-physmap.txt | 1 CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...)
6 - compatible : should contain the specific model of mtd chip(s)
7 used, if known, followed by either "cfi-flash", "jedec-flash",
8 "mtd-ram" or "mtd-rom".
9 - reg : Address range(s) of the mtd chip(s)
11 non-identical chips can be described in one node.
12 - bank-width : Width (in bytes) of the bank. Equal to the
13 device width times the number of interleaved chips.
14 - device-width : (optional) Width of a single mtd chip. If
15 omitted, assumed to be equal to 'bank-width'.
[all …]
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| D | fsmc-nand.txt | 5 - compatible : "st,spear600-fsmc-nand", "stericsson,fsmc-nand"
6 - reg : Address range of the mtd chip
7 - reg-names: Should contain the reg names "fsmc_regs", "nand_data", "nand_addr" and "nand_cmd"
10 - bank-width : Width (in bytes) of the device. If not present, the width
12 - nand-skip-bbtscan: Indicates the BBT scanning should be skipped
13 - timings: array of 6 bytes for NAND timings. The meanings of these bytes
20 kept in Hi-Z (tristate) after the start of a write access.
32 - bank: default NAND bank to use (0-3 are valid, 0 is the default).
33 - nand-ecc-mode : see nand-controller.yaml
34 - nand-ecc-strength : see nand-controller.yaml
[all …]
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| /kernel/linux/linux-5.10/arch/powerpc/boot/dts/ |
| D | media5200.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
12 &gpt0 { fsl,has-wdt; };
24 stdout-path = &console;
29 timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot
30 bus-frequency = <132000000>; // 132 MHz
31 clock-frequency = <396000000>; // 396 MHz
40 bus-frequency = <132000000>;// 132 MHz
64 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
68 phy-handle = <&phy0>;
72 phy0: ethernet-phy@0 {
[all …]
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| /kernel/linux/linux-5.10/drivers/gpio/ |
| D | gpio-brcmstb.c | 2 * Copyright (C) 2015-2017 Broadcom
36 #define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32))) argument
37 #define GIO_ODEN(bank) GIO_BANK_OFF(bank, GIO_REG_ODEN) argument
38 #define GIO_DATA(bank) GIO_BANK_OFF(bank, GIO_REG_DATA) argument
39 #define GIO_IODIR(bank) GIO_BANK_OFF(bank, GIO_REG_IODIR) argument
40 #define GIO_EC(bank) GIO_BANK_OFF(bank, GIO_REG_EC) argument
41 #define GIO_EI(bank) GIO_BANK_OFF(bank, GIO_REG_EI) argument
42 #define GIO_MASK(bank) GIO_BANK_OFF(bank, GIO_REG_MASK) argument
43 #define GIO_LEVEL(bank) GIO_BANK_OFF(bank, GIO_REG_LEVEL) argument
44 #define GIO_STAT(bank) GIO_BANK_OFF(bank, GIO_REG_STAT) argument
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/mtd/ |
| D | mtd-physmap.txt | 1 CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...)
6 - compatible : should contain the specific model of mtd chip(s)
7 used, if known, followed by either "cfi-flash", "jedec-flash",
8 "mtd-ram" or "mtd-rom".
9 - reg : Address range(s) of the mtd chip(s)
11 non-identical chips can be described in one node.
12 - bank-width : Width (in bytes) of the bank. Equal to the
13 device width times the number of interleaved chips.
14 - device-width : (optional) Width of a single mtd chip. If
15 omitted, assumed to be equal to 'bank-width'.
[all …]
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| D | fsmc-nand.txt | 5 - compatible : "st,spear600-fsmc-nand", "stericsson,fsmc-nand"
6 - reg : Address range of the mtd chip
7 - reg-names: Should contain the reg names "fsmc_regs", "nand_data", "nand_addr" and "nand_cmd"
10 - bank-width : Width (in bytes) of the device. If not present, the width
12 - nand-skip-bbtscan: Indicates the BBT scanning should be skipped
13 - timings: array of 6 bytes for NAND timings. The meanings of these bytes
20 kept in Hi-Z (tristate) after the start of a write access.
32 - bank: default NAND bank to use (0-3 are valid, 0 is the default).
33 - nand-ecc-mode : see nand.txt
34 - nand-ecc-strength : see nand.txt
[all …]
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| /kernel/linux/linux-4.19/arch/powerpc/boot/dts/ |
| D | media5200.dts | 16 &gpt0 { fsl,has-wdt; };
28 stdout-path = &console;
33 timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot
34 bus-frequency = <132000000>; // 132 MHz
35 clock-frequency = <396000000>; // 396 MHz
44 bus-frequency = <132000000>;// 132 MHz
68 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
72 phy-handle = <&phy0>;
76 phy0: ethernet-phy@0 {
87 interrupt-map-mask = <0xf800 0 0 7>;
[all …]
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| /kernel/linux/linux-4.19/drivers/gpio/ |
| D | gpio-brcmstb.c | 2 * Copyright (C) 2015-2017 Broadcom
36 #define GIO_BANK_OFF(bank, off) (((bank) * GIO_BANK_SIZE) + (off * sizeof(u32))) argument
37 #define GIO_ODEN(bank) GIO_BANK_OFF(bank, GIO_REG_ODEN) argument
38 #define GIO_DATA(bank) GIO_BANK_OFF(bank, GIO_REG_DATA) argument
39 #define GIO_IODIR(bank) GIO_BANK_OFF(bank, GIO_REG_IODIR) argument
40 #define GIO_EC(bank) GIO_BANK_OFF(bank, GIO_REG_EC) argument
41 #define GIO_EI(bank) GIO_BANK_OFF(bank, GIO_REG_EI) argument
42 #define GIO_MASK(bank) GIO_BANK_OFF(bank, GIO_REG_MASK) argument
43 #define GIO_LEVEL(bank) GIO_BANK_OFF(bank, GIO_REG_LEVEL) argument
44 #define GIO_STAT(bank) GIO_BANK_OFF(bank, GIO_REG_STAT) argument
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/memory-controllers/ |
| D | exynos-srom.txt | 4 - compatible : Should contain "samsung,exynos4210-srom".
6 - reg: offset and length of the register set
12 - #address-cells: Must be set to 2 to allow device address translation.
13 Address is specified as (bank#, offset).
15 - #size-cells: Must be set to 1 to allow device size passing
17 - ranges: Must be set up to reflect the memory layout with four integer values
18 per bank:
19 <bank-number> 0 <parent address of bank> <size>
21 Sub-nodes:
24 properties, describing configuration of the relevant SROM bank:
[all …]
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| /kernel/linux/linux-4.19/drivers/memory/samsung/ |
| D | exynos-srom.c | 1 // SPDX-License-Identifier: GPL-2.0
6 // EXYNOS - SROM Controller support
17 #include "exynos-srom.h"
70 u32 bank, width, pmc = 0; in exynos_srom_configure_bank() local
74 if (of_property_read_u32(np, "reg", &bank)) in exynos_srom_configure_bank()
75 return -EINVAL; in exynos_srom_configure_bank()
76 if (of_property_read_u32(np, "reg-io-width", &width)) in exynos_srom_configure_bank()
77 width = 1; in exynos_srom_configure_bank()
78 if (of_property_read_bool(np, "samsung,srom-page-mode")) in exynos_srom_configure_bank()
80 if (of_property_read_u32_array(np, "samsung,srom-timing", timing, in exynos_srom_configure_bank()
[all …]
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| /kernel/linux/linux-5.10/drivers/memory/samsung/ |
| D | exynos-srom.c | 1 // SPDX-License-Identifier: GPL-2.0
6 // Exynos - SROM Controller support
17 #include "exynos-srom.h"
70 u32 bank, width, pmc = 0; in exynos_srom_configure_bank() local
74 if (of_property_read_u32(np, "reg", &bank)) in exynos_srom_configure_bank()
75 return -EINVAL; in exynos_srom_configure_bank()
76 if (of_property_read_u32(np, "reg-io-width", &width)) in exynos_srom_configure_bank()
77 width = 1; in exynos_srom_configure_bank()
78 if (of_property_read_bool(np, "samsung,srom-page-mode")) in exynos_srom_configure_bank()
80 if (of_property_read_u32_array(np, "samsung,srom-timing", timing, in exynos_srom_configure_bank()
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/memory-controllers/ |
| D | exynos-srom.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/exynos-srom.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
19 - const: samsung,exynos4210-srom
24 "#address-cells":
27 "#size-cells":
32 Reflects the memory layout with four integer values per bank. Format:
33 <bank-number> 0 <parent address of bank> <size>
[all …]
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| /kernel/liteos_m/targets/riscv_nuclei_gd32vf103_soc_gcc/SoC/gd32vf103/Common/Include/ |
| D | gd32vf103_exmc.h | 5 \version 2019-6-5, V1.0.0, firmware for GD32VF103
55 #define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */
56 #define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory addres…
57 #define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR bank memory type */
58 …C_SNCTL_NRW BITS(4,5) /*!< NOR bank memory data bus width */
84 …_region; /*!< select the region of EXMC NOR/SRAM bank */
89 …h; /*!< specifies the databus width of external memory…
99 /* NOR bank memory data bus width */
101 #define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width 8 bits …
102 #define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width 16 bits…
[all …]
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| /kernel/linux/linux-4.19/arch/arm/boot/dts/ |
| D | omap-zoom-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
6 #include "omap-gpmc-smsc911x.dtsi"
20 bank-width = <2>;
21 reg-shift = <1>;
22 reg-io-width = <1>;
23 interrupt-parent = <&gpio4>;
25 clock-frequency = <1843200>;
26 current-speed = <115200>;
27 gpmc,mux-add-data = <0>;
28 gpmc,device-width = <1>;
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | omap-zoom-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
6 #include "omap-gpmc-smsc911x.dtsi"
20 bank-width = <2>;
21 reg-shift = <1>;
22 reg-io-width = <1>;
23 interrupt-parent = <&gpio4>;
25 clock-frequency = <1843200>;
26 current-speed = <115200>;
27 gpmc,mux-add-data = <0>;
28 gpmc,device-width = <1>;
[all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/net/ |
| D | gpmc-eth.txt | 4 General-Purpose Memory Controller can be used to connect Pseudo-SRAM devices
12 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
18 Child nodes need to specify the GPMC bus address width using the "bank-width"
20 specify the I/O registers address width. Even when the GPMC has a maximum 16-bit
21 address width, it supports devices with 32-bit word registers.
23 OMAP2+ board, "bank-width = <2>;" and "reg-io-width = <4>;".
26 - bank-width: Address width of the device in bytes. GPMC supports 8-bit
27 and 16-bit devices and so must be either 1 or 2 bytes.
28 - compatible: Compatible string property for the ethernet child device.
29 - gpmc,cs-on-ns: Chip-select assertion time
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/net/ |
| D | gpmc-eth.txt | 4 General-Purpose Memory Controller can be used to connect Pseudo-SRAM devices
12 Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
18 Child nodes need to specify the GPMC bus address width using the "bank-width"
20 specify the I/O registers address width. Even when the GPMC has a maximum 16-bit
21 address width, it supports devices with 32-bit word registers.
23 OMAP2+ board, "bank-width = <2>;" and "reg-io-width = <4>;".
26 - bank-width: Address width of the device in bytes. GPMC supports 8-bit
27 and 16-bit devices and so must be either 1 or 2 bytes.
28 - compatible: Compatible string property for the ethernet child device.
29 - gpmc,cs-on-ns: Chip-select assertion time
[all …]
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| /kernel/linux/linux-4.19/arch/arm/mach-ks8695/ |
| D | regs-mem.h | 2 * arch/arm/mach-ks8695/include/mach/regs-mem.h
6 * KS8695 - Memory Controller registers and bit definitions
58 #define ERGCON_DSX2 (3 << 20) /* Data Width (External I/O Bank 2) */
59 #define ERGCON_DSX1 (3 << 18) /* Data Width (External I/O Bank 1) */
60 #define ERGCON_DSX0 (3 << 16) /* Data Width (External I/O Bank 0) */
61 #define ERGCON_DSR1 (3 << 2) /* Data Width (ROM/SRAM/Flash Bank 1) */
62 #define ERGCON_DSR0 (3 << 0) /* Data Width (ROM/SRAM/Flash Bank 0) */
69 #define SDCON_DBDBW (3 << 1) /* Data Bus Width */
|
| /kernel/linux/linux-4.19/drivers/pinctrl/sh-pfc/ |
| D | sh_pfc.h | 15 #include <linux/pinctrl/pinconf-generic.h>
107 * Describe a config register consisting of several fields of the same width
108 * - name: Register name (unused, for documentation purposes only)
109 * - r: Physical register address
110 * - r_width: Width of the register (in bits)
111 * - f_width: Width of the fixed-width register fields (in bits)
122 * - name: Register name (unused, for documentation purposes only)
123 * - r: Physical register address
124 * - r_width: Width of the register (in bits)
125 * - var_fw0, var_fwn...: List of widths of the register fields (in bits),
[all …]
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| /kernel/linux/linux-5.10/drivers/clk/qcom/ |
| D | clk-rcg.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
15 #include "clk-rcg.h"
20 ns >>= s->src_sel_shift; in ns_to_src()
30 mask <<= s->src_sel_shift; in src_to_ns()
33 ns |= src << s->src_sel_shift; in src_to_ns()
44 ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); in clk_rcg_get_parent()
47 ns = ns_to_src(&rcg->s, ns); in clk_rcg_get_parent()
49 if (ns == rcg->s.parent_map[i].cfg) in clk_rcg_get_parent()
58 static int reg_to_bank(struct clk_dyn_rcg *rcg, u32 bank) in reg_to_bank() argument
[all …]
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| /kernel/linux/linux-5.10/drivers/pinctrl/renesas/ |
| D | sh_pfc.h | 1 /* SPDX-License-Identifier: GPL-2.0
12 #include <linux/pinctrl/pinconf-generic.h>
119 u16 nr_enum_ids; /* for variable width regs only */
131 * Describe a config register consisting of several fields of the same width
132 * - name: Register name (unused, for documentation purposes only)
133 * - r: Physical register address
134 * - r_width: Width of the register (in bits)
135 * - f_width: Width of the fixed-width register fields (in bits)
136 * - ids: For each register field (from left to right, i.e. MSB to LSB),
151 * - name: Register name (unused, for documentation purposes only)
[all …]
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| /kernel/linux/linux-4.19/drivers/clk/qcom/ |
| D | clk-rcg.c | 18 #include <linux/clk-provider.h>
23 #include "clk-rcg.h"
28 ns >>= s->src_sel_shift; in ns_to_src()
38 mask <<= s->src_sel_shift; in src_to_ns()
41 ns |= src << s->src_sel_shift; in src_to_ns()
52 ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); in clk_rcg_get_parent()
55 ns = ns_to_src(&rcg->s, ns); in clk_rcg_get_parent()
57 if (ns == rcg->s.parent_map[i].cfg) in clk_rcg_get_parent()
66 static int reg_to_bank(struct clk_dyn_rcg *rcg, u32 bank) in reg_to_bank() argument
68 bank &= BIT(rcg->mux_sel_bit); in reg_to_bank()
[all …]
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| /kernel/linux/linux-5.10/drivers/edac/ |
| D | synopsys_edac.c | 5 * Copyright (C) 2012 - 2014 Xilinx, Inc.
154 /* DDR Control Register width definitions */
270 * struct ecc_error_info - ECC error log information.
273 * @bank: Bank number.
276 * @bankgrpnr: Bank group number.
282 u32 bank; member
290 * struct synps_ecc_status - ECC status information to report.
304 * struct synps_edac_priv - DDR memory controller private instance data.
314 * @bank_shift: Bit shifts for bank bit.
315 * @bankgrp_shift: Bit shifts for bank group bit.
[all …]
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