Searched +full:bcm +full:- +full:nsp +full:- +full:smp (Results 1 – 9 of 9) sorted by relevance
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/bcm/ |
| D | brcm,nsp-cpu-method.txt | 2 --------------------------------------------- 9 - enable-method = "brcm,bcm-nsp-smp"; 10 - secondary-boot-reg = <...>; 12 The secondary-boot-reg property is a u32 value that specifies the 15 and should be added per cpu. E.g., in case of NSP (BCM58625) which 21 #address-cells = <1>; 22 #size-cells = <0>; 26 compatible = "arm,cortex-a9"; 27 next-level-cache = <&L2>; 33 compatible = "arm,cortex-a9"; [all …]
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| /kernel/linux/linux-4.19/arch/arm/boot/dts/ |
| D | bcm-nsp.dtsi | 33 #include <dt-bindings/interrupt-controller/arm-gic.h> 34 #include <dt-bindings/interrupt-controller/irq.h> 35 #include <dt-bindings/clock/bcm-nsp.h> 40 compatible = "brcm,nsp"; 42 interrupt-parent = <&gic>; 45 #address-cells = <1>; 46 #size-cells = <0>; 50 compatible = "arm,cortex-a9"; 51 next-level-cache = <&L2>; 57 compatible = "arm,cortex-a9"; [all …]
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| D | bcm4708.dtsi | 5 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de> 20 stdout-path = "serial0:115200n8"; 24 #address-cells = <1>; 25 #size-cells = <0>; 26 enable-method = "brcm,bcm-nsp-smp"; 30 compatible = "arm,cortex-a9"; 31 next-level-cache = <&L2>; 37 compatible = "arm,cortex-a9"; 38 next-level-cache = <&L2>; 39 secondary-boot-reg = <0xffff0400>;
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | bcm-nsp.dtsi | 33 #include <dt-bindings/interrupt-controller/arm-gic.h> 34 #include <dt-bindings/interrupt-controller/irq.h> 35 #include <dt-bindings/clock/bcm-nsp.h> 38 #address-cells = <1>; 39 #size-cells = <1>; 40 compatible = "brcm,nsp"; 42 interrupt-parent = <&gic>; 53 #address-cells = <1>; 54 #size-cells = <0>; 58 compatible = "arm,cortex-a9"; [all …]
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| D | bcm4708.dtsi | 5 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de> 20 stdout-path = "serial0:115200n8"; 24 #address-cells = <1>; 25 #size-cells = <0>; 26 enable-method = "brcm,bcm-nsp-smp"; 30 compatible = "arm,cortex-a9"; 31 next-level-cache = <&L2>; 37 compatible = "arm,cortex-a9"; 38 next-level-cache = <&L2>; 39 secondary-boot-reg = <0xffff0400>;
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/ |
| D | cpus.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> 21 with updates for 32-bit and 64-bit ARM systems provided in this document. 30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in 59 On 32-bit ARM v7 or later systems this property is 68 On ARM v8 64-bit systems this property is required 71 * If cpus node's #address-cells property is set to 2 79 * If cpus node's #address-cells property is set to 1 [all …]
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| /kernel/linux/linux-5.10/arch/arm/mach-bcm/ |
| D | platsmp.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (C) 2014-2015 Broadcom Corporation 12 #include <linux/irqchip/irq-bcm2836.h> 18 #include <linux/smp.h> 21 #include <asm/smp.h> 34 #define OF_SECONDARY_BOOT "secondary-boot-reg" 54 return -ENXIO; in scu_a9_enable() 61 return -ENOENT; in scu_a9_enable() 68 return -ENOMEM; in scu_a9_enable() 106 return -EINVAL; in nsp_write_lut() [all …]
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| /kernel/linux/linux-4.19/arch/arm/mach-bcm/ |
| D | platsmp.c | 2 * Copyright (C) 2014-2015 Broadcom Corporation 20 #include <linux/irqchip/irq-bcm2836.h> 26 #include <linux/smp.h> 29 #include <asm/smp.h> 40 #define OF_SECONDARY_BOOT "secondary-boot-reg" 60 return -ENXIO; in scu_a9_enable() 67 return -ENOENT; in scu_a9_enable() 74 return -ENOMEM; in scu_a9_enable() 112 return -EINVAL; in nsp_write_lut() 117 pr_warn("unable to ioremap SKU-ROM LUT register for cpu %u\n", cpu); in nsp_write_lut() [all …]
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/ |
| D | cpus.txt | 13 with updates for 32-bit and 64-bit ARM systems provided in this document. 22 - square brackets define bitfields, eg reg[7:0] value of the bitfield in 33 - cpus node 41 - #address-cells 52 # On 32-bit ARM 11 MPcore, ARM v7 or later systems 55 # On ARM v8 64-bit systems value should be set to 2, 58 in the system, #address-cells can be set to 1, since 61 - #size-cells 66 - cpu node 72 - device_type [all …]
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