| /kernel/linux/linux-5.10/arch/arm64/boot/dts/amazon/ |
| D | alpine-v3.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "amazon,al-alpine-v3";
14 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a72";
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/ti/ |
| D | k3-am654.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
8 #include "k3-am65.dtsi"
12 #address-cells = <1>;
13 #size-cells = <0>;
14 cpu-map {
37 compatible = "arm,cortex-a53";
40 enable-method = "psci";
41 i-cache-size = <0x8000>;
42 i-cache-line-size = <64>;
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| /kernel/linux/linux-4.19/arch/arm64/boot/dts/ti/ |
| D | k3-am654.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
8 #include "k3-am65.dtsi"
12 #address-cells = <1>;
13 #size-cells = <0>;
14 cpu-map {
37 compatible = "arm,cortex-a53", "arm,armv8";
40 enable-method = "psci";
41 i-cache-size = <0x8000>;
42 i-cache-line-size = <64>;
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/marvell/ |
| D | armada-ap806-quad.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-ap806.dtsi"
12 compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806";
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-a72";
22 enable-method = "psci";
23 #cooling-cells = <2>;
25 i-cache-size = <0xc000>;
26 i-cache-line-size = <64>;
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| D | armada-ap807-quad.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-ap807.dtsi"
12 compatible = "marvell,armada-ap807-quad", "marvell,armada-ap807";
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-a72";
22 enable-method = "psci";
23 #cooling-cells = <2>;
25 i-cache-size = <0xc000>;
26 i-cache-line-size = <64>;
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| D | armada-ap806-dual.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include "armada-ap806.dtsi"
12 compatible = "marvell,armada-ap806-dual", "marvell,armada-ap806";
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-a72";
22 enable-method = "psci";
23 #cooling-cells = <2>;
25 i-cache-size = <0xc000>;
26 i-cache-line-size = <64>;
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/arm/ |
| D | juno-r2.dts | 9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
13 #include "juno-cs-r1r2.dtsi"
17 compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
27 stdout-path = "serial0:115200n8";
31 compatible = "arm,psci-0.2";
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| D | juno.dts | 4 * Copyright (c) 2013-2014 ARM Ltd.
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
26 stdout-path = "serial0:115200n8";
30 compatible = "arm,psci-0.2";
35 #address-cells = <2>;
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| D | juno-r1.dts | 9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
13 #include "juno-cs-r1r2.dtsi"
17 compatible = "arm,juno-r1", "arm,juno", "arm,vexpress";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
27 stdout-path = "serial0:115200n8";
31 compatible = "arm,psci-0.2";
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| /kernel/linux/linux-4.19/arch/arm64/boot/dts/arm/ |
| D | juno-r2.dts | 9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
13 #include "juno-cs-r1r2.dtsi"
17 compatible = "arm,juno-r2", "arm,juno", "arm,vexpress";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
27 stdout-path = "serial0:115200n8";
31 compatible = "arm,psci-0.2";
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| D | juno-r1.dts | 9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
13 #include "juno-cs-r1r2.dtsi"
17 compatible = "arm,juno-r1", "arm,juno", "arm,vexpress";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
27 stdout-path = "serial0:115200n8";
31 compatible = "arm,psci-0.2";
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| D | juno.dts | 4 * Copyright (c) 2013-2014 ARM Ltd.
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
26 stdout-path = "serial0:115200n8";
30 compatible = "arm,psci-0.2";
35 #address-cells = <2>;
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/uniphier/ |
| D | cache-uniphier.txt | 1 UniPhier outer cache controller
3 UniPhier SoCs are integrated with a full-custom outer cache controller system.
4 All of them have a level 2 cache controller, and some have a level 3 cache
8 - compatible: should be "socionext,uniphier-system-cache"
9 - reg: offsets and lengths of the register sets for the device. It should
12 - cache-unified: specifies the cache is a unified cache.
13 - cache-size: specifies the size in bytes of the cache
14 - cache-sets: specifies the number of associativity sets of the cache
15 - cache-line-size: specifies the line size in bytes
16 - cache-level: specifies the level in the cache hierarchy. The value should
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| /kernel/linux/linux-4.19/arch/powerpc/kernel/ |
| D | cacheinfo.c | 2 * Processor cache information made available to userspace via sysfs;
26 /* per-cpu object for tracking:
27 * - a "cache" kobject for the top-level directory
28 * - a list of "index" objects representing the cpu's local cache hierarchy
31 struct kobject *kobj; /* bare (not embedded) kobject for cache
36 /* "index" object: each cpu's cache directory has an index
37 * subdirectory corresponding to a cache object associated with the
43 struct cache *cache; member
47 * cache type */
52 /* Allow for both [di]-cache-line-size and
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/socionext/ |
| D | socionext,uniphier-system-cache.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/socionext/socionext,uniphier-system-cache.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UniPhier outer cache controller
10 UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache
11 controller system. All of them have a level 2 cache controller, and some
12 have a level 3 cache controller as well.
15 - Masahiro Yamada <yamada.masahiro@socionext.com>
19 const: socionext,uniphier-system-cache
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| /kernel/linux/linux-5.10/arch/powerpc/kernel/ |
| D | cacheinfo.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Processor cache information made available to userspace via sysfs;
27 /* per-cpu object for tracking:
28 * - a "cache" kobject for the top-level directory
29 * - a list of "index" objects representing the cpu's local cache hierarchy
32 struct kobject *kobj; /* bare (not embedded) kobject for cache
37 /* "index" object: each cpu's cache directory has an index
38 * subdirectory corresponding to a cache object associated with the
44 struct cache *cache; member
48 * cache type */
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/ |
| D | fsl-lx2160a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Device Tree Include file for Layerscape-LX2160A family SoC.
5 // Copyright 2018-2020 NXP
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
24 #address-cells = <1>;
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | l2cache.txt | 1 Freescale L2 Cache Controller
3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
4 The cache bindings explained below are Devicetree Specification compliant
8 - compatible : Should include one of the following:
9 "fsl,8540-l2-cache-controller"
10 "fsl,8541-l2-cache-controller"
11 "fsl,8544-l2-cache-controller"
12 "fsl,8548-l2-cache-controller"
13 "fsl,8555-l2-cache-controller"
14 "fsl,8568-l2-cache-controller"
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | l2cache.txt | 1 Freescale L2 Cache Controller
3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
4 The cache bindings explained below are Devicetree Specification compliant
8 - compatible : Should include one of the following:
9 "fsl,8540-l2-cache-controller"
10 "fsl,8541-l2-cache-controller"
11 "fsl,8544-l2-cache-controller"
12 "fsl,8548-l2-cache-controller"
13 "fsl,8555-l2-cache-controller"
14 "fsl,8568-l2-cache-controller"
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| /kernel/linux/linux-5.10/arch/riscv/boot/dts/sifive/ |
| D | fu540-c000.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
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| /kernel/linux/linux-5.10/arch/riscv/kernel/ |
| D | cacheinfo.c | 1 // SPDX-License-Identifier: GPL-2.0-only
22 if (rv_cache_ops && rv_cache_ops->get_priv_group) in cache_get_priv_group()
23 return rv_cache_ops->get_priv_group(this_leaf); in cache_get_priv_group()
32 * that cores have a homonogenous view of the cache hierarchy. That in get_cacheinfo()
33 * happens to be the case for the current set of RISC-V systems, but in get_cacheinfo()
42 for (index = 0; index < this_cpu_ci->num_leaves; index++) { in get_cacheinfo()
43 this_leaf = this_cpu_ci->info_list + index; in get_cacheinfo()
44 if (this_leaf->level == level && this_leaf->type == type) in get_cacheinfo()
55 return this_leaf ? this_leaf->size : 0; in get_cache_size()
62 return this_leaf ? (this_leaf->ways_of_associativity << 16 | in get_cache_geometry()
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| /kernel/linux/linux-4.19/mm/kasan/ |
| D | kasan.c | 7 * Some code borrowed from https://github.com/xairy/kasan-prototype by
45 current->kasan_depth++; in kasan_enable_current()
50 current->kasan_depth--; in kasan_disable_current()
54 * Poisons the shadow memory for 'size' bytes starting from 'addr'.
57 static void kasan_poison_shadow(const void *address, size_t size, u8 value) in kasan_poison_shadow() argument
62 shadow_end = kasan_mem_to_shadow(address + size); in kasan_poison_shadow()
64 memset(shadow_start, value, shadow_end - shadow_start); in kasan_poison_shadow()
67 void kasan_unpoison_shadow(const void *address, size_t size) in kasan_unpoison_shadow() argument
69 kasan_poison_shadow(address, size, 0); in kasan_unpoison_shadow()
71 if (size & KASAN_SHADOW_MASK) { in kasan_unpoison_shadow()
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| /kernel/linux/linux-4.19/lib/ |
| D | test_kasan.c | 33 size_t size = 123; in kmalloc_oob_right() local
35 pr_info("out-of-bounds to right\n"); in kmalloc_oob_right()
36 ptr = kmalloc(size, GFP_KERNEL); in kmalloc_oob_right()
42 ptr[size] = 'x'; in kmalloc_oob_right()
49 size_t size = 15; in kmalloc_oob_left() local
51 pr_info("out-of-bounds to left\n"); in kmalloc_oob_left()
52 ptr = kmalloc(size, GFP_KERNEL); in kmalloc_oob_left()
58 *ptr = *(ptr - 1); in kmalloc_oob_left()
65 size_t size = 4096; in kmalloc_node_oob_right() local
67 pr_info("kmalloc_node(): out-of-bounds to right\n"); in kmalloc_node_oob_right()
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| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/ |
| D | l2c2x0.txt | 1 * ARM L2 Cache Controller
4 PL310 and variants) based level 2 cache controller. All these various implementations
5 of the L2 cache controller have compatible programming models (Note 1).
6 Some of the properties that are just prefixed "cache-*" are taken from section
10 The ARM L2 cache representation in the device tree should be done as follows:
14 - compatible : should be one of:
15 "arm,pl310-cache"
16 "arm,l220-cache"
17 "arm,l210-cache"
18 "bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
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| /kernel/linux/linux-4.19/arch/riscv/kernel/ |
| D | cacheinfo.c | 23 this_leaf->level = level; in ci_leaf_init()
24 this_leaf->type = type; in ci_leaf_init()
25 /* not a sector cache */ in ci_leaf_init()
26 this_leaf->physical_line_partition = 1; in ci_leaf_init()
28 this_leaf->attributes = in ci_leaf_init()
40 if (of_property_read_bool(np, "cache-size")) in __init_cache_level()
42 if (of_property_read_bool(np, "i-cache-size")) in __init_cache_level()
44 if (of_property_read_bool(np, "d-cache-size")) in __init_cache_level()
50 if (!of_device_is_compatible(np, "cache")) in __init_cache_level()
52 if (of_property_read_u32(np, "cache-level", &level)) in __init_cache_level()
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