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/kernel/linux/linux-4.19/drivers/fpga/
Dzynq-fpga.c2 * Copyright (c) 2011-2015 Xilinx Inc.
18 #include <linux/clk.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/fpga/fpga-mgr.h>
132 struct clk *clk; member
148 writel(val, priv->io_base + offset); in zynq_fpga_write()
154 return readl(priv->io_base + offset); in zynq_fpga_read()
158 readl_poll_timeout(priv->io_base + addr, val, cond, sleep_us, \
174 first = priv->dma_elm == 0; in zynq_step_dma()
175 while (priv->cur_sg) { in zynq_step_dma()
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Dsocfpga-a10.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2016 Altera Corporation
7 #include <linux/clk.h>
10 #include <linux/fpga/fpga-mgr.h>
65 * struct a10_fpga_priv - private data for fpga manager
68 * @clk: clock
73 struct clk *clk; member
123 regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_02_OFST, in socfpga_a10_fpga_set_cfg_width()
133 regmap_write(priv->regmap, A10_FPGAMGR_DCLKSTAT_OFST, in socfpga_a10_fpga_generate_dclks()
137 regmap_write(priv->regmap, A10_FPGAMGR_DCLKCNT_OFST, count); in socfpga_a10_fpga_generate_dclks()
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/kernel/linux/linux-5.10/drivers/fpga/
Dzynq-fpga.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2011-2015 Xilinx Inc.
10 #include <linux/clk.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/fpga/fpga-mgr.h>
124 struct clk *clk; member
140 writel(val, priv->io_base + offset); in zynq_fpga_write()
146 return readl(priv->io_base + offset); in zynq_fpga_read()
150 readl_poll_timeout(priv->io_base + addr, val, cond, sleep_us, \
166 first = priv->dma_elm == 0; in zynq_step_dma()
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Dsocfpga-a10.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2016 Altera Corporation
7 #include <linux/clk.h>
10 #include <linux/fpga/fpga-mgr.h>
65 * struct a10_fpga_priv - private data for fpga manager
68 * @clk: clock
73 struct clk *clk; member
123 regmap_update_bits(priv->regmap, A10_FPGAMGR_IMGCFG_CTL_02_OFST, in socfpga_a10_fpga_set_cfg_width()
133 regmap_write(priv->regmap, A10_FPGAMGR_DCLKSTAT_OFST, in socfpga_a10_fpga_generate_dclks()
137 regmap_write(priv->regmap, A10_FPGAMGR_DCLKCNT_OFST, count); in socfpga_a10_fpga_generate_dclks()
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/altera/
Dsocfpga-clk-manager.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/altera/socfpga-clk-manager.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dinh Nguyen <dinguyen@kernel.org>
17 - const: altr,clk-mgr
22 - compatible
27 - |
29 compatible = "altr,clk-mgr";
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/altera/
Dsocfpga-clk-manager.txt4 - compatible : "altr,clk-mgr"
5 - reg : Should contain base address and length for Clock Manager
9 compatible = "altr,clk-mgr";
/kernel/linux/linux-5.10/drivers/video/fbdev/omap2/omapfb/dss/
Dvenc.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/clk.h>
249 struct clk *tv_dac_clk;
273 venc_write_reg(VENC_LLEN, config->llen); in venc_write_config()
274 venc_write_reg(VENC_FLENS, config->flens); in venc_write_config()
275 venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr); in venc_write_config()
276 venc_write_reg(VENC_C_PHASE, config->c_phase); in venc_write_config()
277 venc_write_reg(VENC_GAIN_U, config->gain_u); in venc_write_config()
278 venc_write_reg(VENC_GAIN_V, config->gain_v); in venc_write_config()
279 venc_write_reg(VENC_GAIN_Y, config->gain_y); in venc_write_config()
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Ddss.h1 /* SPDX-License-Identifier: GPL-2.0-only */
59 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
105 * Type-A PLLs: clkout[]/mX[] refer to hsdiv outputs m4, m5, m6, m7.
106 * Type-B PLLs: clkout[0] refers to m2.
152 struct clk *clkin;
210 int dss_mgr_simple_check(struct omap_overlay_manager *mgr,
212 int dss_mgr_check_timings(struct omap_overlay_manager *mgr,
214 int dss_mgr_check(struct omap_overlay_manager *mgr,
229 int dss_manager_kobj_init(struct omap_overlay_manager *mgr,
231 void dss_manager_kobj_uninit(struct omap_overlay_manager *mgr);
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/kernel/linux/linux-4.19/drivers/video/fbdev/omap2/omapfb/dss/
Dvenc.c26 #include <linux/clk.h>
236 .llen = 864-1,
237 .flens = 625-1,
303 struct clk *tv_dac_clk;
327 venc_write_reg(VENC_LLEN, config->llen); in venc_write_config()
328 venc_write_reg(VENC_FLENS, config->flens); in venc_write_config()
329 venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr); in venc_write_config()
330 venc_write_reg(VENC_C_PHASE, config->c_phase); in venc_write_config()
331 venc_write_reg(VENC_GAIN_U, config->gain_u); in venc_write_config()
332 venc_write_reg(VENC_GAIN_V, config->gain_v); in venc_write_config()
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Ddss.h70 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
127 * Type-A PLLs: clkout[]/mX[] refer to hsdiv outputs m4, m5, m6, m7.
128 * Type-B PLLs: clkout[0] refers to m2.
174 struct clk *clkin;
232 int dss_mgr_simple_check(struct omap_overlay_manager *mgr,
234 int dss_mgr_check_timings(struct omap_overlay_manager *mgr,
236 int dss_mgr_check(struct omap_overlay_manager *mgr,
251 int dss_manager_kobj_init(struct omap_overlay_manager *mgr,
253 void dss_manager_kobj_uninit(struct omap_overlay_manager *mgr);
258 void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr);
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Drfbi.c26 #include <linux/dma-mapping.h>
29 #include <linux/clk.h>
140 r = pm_runtime_get_sync(&rfbi.pdev->dev); in rfbi_runtime_get()
151 r = pm_runtime_put_sync(&rfbi.pdev->dev); in rfbi_runtime_put()
152 WARN_ON(r < 0 && r != -ENOSYS); in rfbi_runtime_put()
171 for (; len; len--) in rfbi_write_command()
180 for (; len; len -= 2) in rfbi_write_command()
198 for (; len; len--) { in rfbi_read_data()
209 for (; len; len -= 2) { in rfbi_read_data()
229 for (; len; len--) in rfbi_write_data()
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/kernel/linux/linux-4.19/arch/arm/boot/dts/
Dsocfpga_arria10.dtsi17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
21 #address-cells = <1>;
22 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <0>;
27 enable-method = "altr,socfpga-a10-smp";
30 compatible = "arm,cortex-a9";
33 next-level-cache = <&L2>;
36 compatible = "arm,cortex-a9";
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Dsocfpga.dtsi18 #include <dt-bindings/reset/altr,rst-mgr.h>
21 #address-cells = <1>;
22 #size-cells = <1>;
36 #address-cells = <1>;
37 #size-cells = <0>;
38 enable-method = "altr,socfpga-smp";
41 compatible = "arm,cortex-a9";
44 next-level-cache = <&L2>;
47 compatible = "arm,cortex-a9";
50 next-level-cache = <&L2>;
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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dsocfpga_arria10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
[all …]
Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "altr,socfpga-smp";
27 compatible = "arm,cortex-a9";
30 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9";
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/kernel/linux/linux-5.10/drivers/clk/socfpga/
Dclk-gate-a10.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
12 #include "clk.h"
27 if (socfpgaclk->fixed_div) in socfpga_gate_clk_recalc_rate()
28 div = socfpgaclk->fixed_div; in socfpga_gate_clk_recalc_rate()
29 else if (socfpgaclk->div_reg) { in socfpga_gate_clk_recalc_rate()
30 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_gate_clk_recalc_rate()
31 val &= GENMASK(socfpgaclk->width - 1, 0); in socfpga_gate_clk_recalc_rate()
45 if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) { in socfpga_clk_prepare()
47 switch (socfpgaclk->clk_phase[i]) { in socfpga_clk_prepare()
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Dclk-gate.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011-2012 Calxeda, Inc.
4 * Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
6 * Based from clk-highbank.c
9 #include <linux/clk-provider.h>
15 #include "clk.h"
96 if (socfpgaclk->fixed_div) in socfpga_clk_recalc_rate()
97 div = socfpgaclk->fixed_div; in socfpga_clk_recalc_rate()
98 else if (socfpgaclk->div_reg) { in socfpga_clk_recalc_rate()
99 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_clk_recalc_rate()
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Dclk-pll-a10.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
11 #include "clk.h"
42 reg = readl(socfpgaclk->hw.reg + 0x4); in clk_pll_recalc_rate()
55 pll_src = readl(socfpgaclk->hw.reg); in clk_pll_get_parent()
66 static struct clk * __init __socfpga_pll_init(struct device_node *node, in __socfpga_pll_init()
70 struct clk *clk; in __socfpga_pll_init() local
72 const char *clk_name = node->name; in __socfpga_pll_init()
85 clkmgr_np = of_find_compatible_node(NULL, NULL, "altr,clk-mgr"); in __socfpga_pll_init()
89 pll_clk->hw.reg = clk_mgr_a10_base_addr + reg; in __socfpga_pll_init()
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Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011-2012 Calxeda, Inc.
4 * Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
6 * Based from clk-highbank.c
9 #include <linux/clk-provider.h>
14 #include "clk.h"
46 reg = readl(socfpgaclk->hw.reg); in clk_pll_recalc_rate()
63 pll_src = readl(socfpgaclk->hw.reg); in clk_pll_get_parent()
73 static __init struct clk *__socfpga_pll_init(struct device_node *node, in __socfpga_pll_init()
77 struct clk *clk; in __socfpga_pll_init() local
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/kernel/linux/linux-4.19/drivers/clk/socfpga/
Dclk-gate-a10.c17 #include <linux/clk-provider.h>
23 #include "clk.h"
38 if (socfpgaclk->fixed_div) in socfpga_gate_clk_recalc_rate()
39 div = socfpgaclk->fixed_div; in socfpga_gate_clk_recalc_rate()
40 else if (socfpgaclk->div_reg) { in socfpga_gate_clk_recalc_rate()
41 val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; in socfpga_gate_clk_recalc_rate()
42 val &= GENMASK(socfpgaclk->width - 1, 0); in socfpga_gate_clk_recalc_rate()
56 if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) { in socfpga_clk_prepare()
58 switch (socfpgaclk->clk_phase[i]) { in socfpga_clk_prepare()
90 if (!IS_ERR(socfpgaclk->sys_mgr_base_addr)) in socfpga_clk_prepare()
[all …]
Dclk-gate.c2 * Copyright 2011-2012 Calxeda, Inc.
3 * Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
15 * Based from clk-highbank.c
19 #include <linux/clk-provider.h>
25 #include "clk.h"
44 if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) { in socfpga_clk_get_parent()
48 if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) { in socfpga_clk_get_parent()
54 if (streq(hwclk->init->name, SOCFPGA_MMC_CLK)) in socfpga_clk_get_parent()
56 if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) || in socfpga_clk_get_parent()
57 streq(hwclk->init->name, SOCFPGA_NAND_X_CLK)) in socfpga_clk_get_parent()
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/intel/
Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/agilex-clock.h>
12 compatible = "intel,socfpga-agilex";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/altera/
Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
[all …]
/kernel/linux/linux-5.10/include/video/
Domapfb_dss.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
88 OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
91 OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
92 OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
93 OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
94 OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
99 OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */
100 OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */
101 OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */
102 OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */
[all …]
/kernel/linux/linux-4.19/include/video/
Domapfb_dss.h92 OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
95 OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
96 OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
97 OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
98 OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
103 OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */
104 OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */
105 OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */
106 OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */
373 struct omap_overlay_manager *mgr);
[all …]

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