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/kernel/linux/linux-5.10/drivers/clk/mediatek/
DKconfig20 This driver supports MediaTek MT2701 basic clocks.
26 This driver supports MediaTek MT2701 mmsys clocks.
32 This driver supports MediaTek MT2701 imgsys clocks.
38 This driver supports MediaTek MT2701 vdecsys clocks.
44 This driver supports MediaTek MT2701 hifsys clocks.
50 This driver supports MediaTek MT2701 ethsys clocks.
56 This driver supports MediaTek MT2701 bdpsys clocks.
62 This driver supports Mediatek MT2701 audsys clocks.
68 This driver supports MediaTek MT2701 g3dsys clocks.
76 This driver supports MediaTek MT2712 basic clocks.
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/clock/
Drenesas,cpg-mstp-clocks.txt1 * Renesas CPG Module Stop (MSTP) Clocks
3 The CPG can gate SoC device clocks. The gates are organized in groups of up to
6 This device tree binding describes a single 32 gate clocks group per node.
7 Clocks are referenced by user nodes by the MSTP node phandle and the clock
13 - "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks
14 - "renesas,r8a73a4-mstp-clocks" for R8A73A4 (R-Mobile APE6) MSTP gate clocks
15 - "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks
16 - "renesas,r8a7778-mstp-clocks" for R8A7778 (R-Car M1) MSTP gate clocks
17 - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
18 - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
[all …]
Dexynos5433-clock.txt10 which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS
11 domains and bus clocks.
13 which generates clocks for LLI (Low Latency Interface) IP.
15 which generates clocks for DRAM Memory Controller domain.
17 which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs.
19 which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs.
21 which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
23 which generates clocks for G2D/MDMA IPs.
25 which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
27 which generates clocks for Cortex-A5/BUS/AUDIO clocks.
[all …]
Dexynos5260-clock.txt5 generate and supply clocks to various hardware blocks within
10 available clocks are defined as preprocessor macros in
14 External clocks:
16 There are several clocks that are generated outside the SoC. It
26 Phy clocks:
28 There are several clocks which are generated by specific PHYs.
29 These clocks are fed into the clock controller and then routed to
30 the hardware blocks. These clocks are defined as fixed clocks in the
71 - clocks: list of clock identifiers which are fed as the input to
73 the input clocks for a given controller.
[all …]
/kernel/linux/linux-4.19/arch/arm/boot/dts/
Ds5pv210.dtsi59 external-clocks {
88 clocks = <&clocks CLK_NANDXL>, <&clocks DOUT_FLASH>;
100 clocks: clock-controller@e0100000 { label
104 clocks = <&xxti>, <&xusbxti>;
131 clocks = <&clocks CLK_PDMA0>;
143 clocks = <&clocks CLK_PDMA1>;
157 clocks = <&clocks SCLK_SPI0>, <&clocks CLK_SPI0>;
173 clocks = <&clocks SCLK_SPI1>, <&clocks CLK_SPI1>;
187 clocks = <&clocks CLK_KEYIF>;
197 clocks = <&clocks CLK_I2C0>;
[all …]
Ds3c2416.dtsi30 clocks: clock-controller@4c000000 { label
41 clocks = <&clocks PCLK_PWM>;
49 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
50 <&clocks SCLK_UART>;
57 clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>,
58 <&clocks SCLK_UART>;
65 clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>,
66 <&clocks SCLK_UART>;
75 clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>,
76 <&clocks SCLK_UART>;
[all …]
Domap3xxx-clocks.dtsi20 …clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck…
27 clocks = <&osc_sys_ck>;
37 clocks = <&osc_sys_ck>;
45 clocks = <&dpll3_ck>;
53 clocks = <&dpll3_m2_ck>;
61 clocks = <&dpll4_ck>;
69 clocks = <&dpll3_m2x2_ck>;
77 clocks = <&sys_ck>;
87 clocks = <&core_96m_fck>, <&mcbsp_clks>;
95 clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
[all …]
Domap24xx-clocks.dtsi14 clocks = <&func_96m_ck>, <&mcbsp_clks>;
22 clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
28 clocks = <&func_96m_ck>, <&mcbsp_clks>;
36 clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>;
80 clocks = <&virt_19200000_ck>, <&virt_26m_ck>, <&virt_13m_ck>, <&virt_12m_ck>;
88 clocks = <&aplls_clkin_ck>;
96 clocks = <&aplls_clkin_ck>, <&aplls_clkin_x2_ck>;
105 clocks = <&osc_ck>;
127 clocks = <&sys_ck>, <&sys_ck>;
134 clocks = <&sys_ck>;
[all …]
Ds3c64xx.dtsi68 clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>,
69 <&clocks SCLK_MMC0>;
79 clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>,
80 <&clocks SCLK_MMC1>;
90 clocks = <&clocks HCLK_HSMMC2>, <&clocks HCLK_HSMMC2>,
91 <&clocks SCLK_MMC2>;
101 clocks = <&clocks PCLK_WDT>;
110 clocks = <&clocks PCLK_IIC0>;
123 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
124 <&clocks SCLK_UART>;
[all …]
Dam43xx-clocks.dtsi14 clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>;
22 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
30 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
38 clocks = <&sys_clkin_ck>;
46 clocks = <&sys_clkin_ck>;
54 clocks = <&sys_clkin_ck>;
62 clocks = <&sys_clkin_ck>;
70 clocks = <&sys_clkin_ck>;
78 clocks = <&sys_clkin_ck>;
86 clocks = <&sys_clkin_ck>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Ds3c2416.dtsi31 clocks: clock-controller@4c000000 { label
43 clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>,
44 <&clocks SCLK_UART>;
54 clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>,
55 <&clocks MUX_HSMMC0>;
65 clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>,
66 <&clocks MUX_HSMMC1>;
73 clocks = <&clocks PCLK_I2C0>;
87 clocks = <&clocks PCLK_RTC>;
92 clocks = <&clocks PCLK_PWM>;
[all …]
Ds5pv210.dtsi82 clocks = <&clocks CLK_NANDXL>, <&clocks DOUT_FLASH>;
94 clocks: clock-controller@e0100000 { label
98 clocks = <&xxti>, <&xusbxti>;
125 clocks = <&clocks CLK_PDMA0>;
137 clocks = <&clocks CLK_PDMA1>;
149 clocks = <&clocks CLK_TSADC>;
163 clocks = <&clocks SCLK_SPI0>, <&clocks CLK_SPI0>;
179 clocks = <&clocks SCLK_SPI1>, <&clocks CLK_SPI1>;
193 clocks = <&clocks CLK_KEYIF>;
203 clocks = <&clocks CLK_I2C0>;
[all …]
Domap3xxx-clocks.dtsi17 …clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck…
24 clocks = <&osc_sys_ck>;
34 clocks = <&osc_sys_ck>;
42 clocks = <&dpll3_ck>;
50 clocks = <&dpll3_m2_ck>;
58 clocks = <&dpll4_ck>;
66 clocks = <&dpll3_m2x2_ck>;
74 clocks = <&sys_ck>;
84 clocks = <&core_96m_fck>, <&mcbsp_clks>;
92 clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
[all …]
Domap24xx-clocks.dtsi11 clocks = <&func_96m_ck>, <&mcbsp_clks>;
19 clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
25 clocks = <&func_96m_ck>, <&mcbsp_clks>;
33 clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>;
77 clocks = <&virt_19200000_ck>, <&virt_26m_ck>, <&virt_13m_ck>, <&virt_12m_ck>;
85 clocks = <&aplls_clkin_ck>;
93 clocks = <&aplls_clkin_ck>, <&aplls_clkin_x2_ck>;
102 clocks = <&osc_ck>;
124 clocks = <&sys_ck>, <&sys_ck>;
131 clocks = <&sys_ck>;
[all …]
Ds3c64xx.dtsi68 clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>,
69 <&clocks SCLK_MMC0>;
79 clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>,
80 <&clocks SCLK_MMC1>;
90 clocks = <&clocks HCLK_HSMMC2>, <&clocks HCLK_HSMMC2>,
91 <&clocks SCLK_MMC2>;
101 clocks = <&clocks PCLK_WDT>;
110 clocks = <&clocks PCLK_IIC0>;
123 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
124 <&clocks SCLK_UART>;
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/xilinx/
Dzynqmp-clk-ccf.dtsi44 clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
48 clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;
52 clocks = <&zynqmp_clk ACPU>;
56 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
60 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
64 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
68 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
72 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
76 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
80 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
[all …]
/kernel/linux/linux-4.19/arch/arm64/boot/dts/xilinx/
Dzynqmp-clk.dtsi76 clocks = <&clk100 &clk100>;
80 clocks = <&clk100 &clk100>;
84 clocks = <&clk600>, <&clk100>;
88 clocks = <&clk600>, <&clk100>;
92 clocks = <&clk600>, <&clk100>;
96 clocks = <&clk600>, <&clk100>;
100 clocks = <&clk600>, <&clk100>;
104 clocks = <&clk600>, <&clk100>;
108 clocks = <&clk600>, <&clk100>;
112 clocks = <&clk600>, <&clk100>;
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/
Dexynos5433-clock.txt10 which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS
11 domains and bus clocks.
13 which generates clocks for LLI (Low Latency Interface) IP.
15 which generates clocks for DRAM Memory Controller domain.
17 which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs.
19 which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs.
21 which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
23 which generates clocks for G2D/MDMA IPs.
25 which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
27 which generates clocks for Cortex-A5/BUS/AUDIO clocks.
[all …]
Dexynos5260-clock.txt5 generate and supply clocks to various hardware blocks within
10 available clocks are defined as preprocessor macros in
14 External clocks:
16 There are several clocks that are generated outside the SoC. It
26 Phy clocks:
28 There are several clocks which are generated by specific PHYs.
29 These clocks are fed into the clock controller and then routed to
30 the hardware blocks. These clocks are defined as fixed clocks in the
71 - clocks: list of clock identifiers which are fed as the input to
73 the input clocks for a given controller.
[all …]
Drenesas,cpg-clocks.yaml4 $id: http://devicetree.org/schemas/clock/renesas,cpg-clocks.yaml#
13 The Clock Pulse Generator (CPG) generates core clocks for the SoC. It
17 the CPG Module Stop (MSTP) Clocks.
22 - const: renesas,r8a73a4-cpg-clocks # R-Mobile APE6
23 - const: renesas,r8a7740-cpg-clocks # R-Mobile A1
24 - const: renesas,r8a7778-cpg-clocks # R-Car M1
25 - const: renesas,r8a7779-cpg-clocks # R-Car H1
28 - renesas,r7s72100-cpg-clocks # RZ/A1H
29 - const: renesas,rz-cpg-clocks # RZ/A1
30 - const: renesas,sh73a0-cpg-clocks # SH-Mobile AG5
[all …]
/kernel/linux/linux-4.19/drivers/clk/mediatek/
DKconfig19 This driver supports MediaTek MT2701 basic clocks.
25 This driver supports MediaTek MT2701 mmsys clocks.
31 This driver supports MediaTek MT2701 imgsys clocks.
37 This driver supports MediaTek MT2701 vdecsys clocks.
43 This driver supports MediaTek MT2701 hifsys clocks.
49 This driver supports MediaTek MT2701 ethsys clocks.
55 This driver supports MediaTek MT2701 bdpsys clocks.
61 This driver supports Mediatek MT2701 audsys clocks.
67 This driver supports MediaTek MT2701 g3dsys clocks.
75 This driver supports MediaTek MT2712 basic clocks.
[all …]
/kernel/linux/linux-4.19/Documentation/devicetree/bindings/display/
Dst,stih4xx.txt15 - clocks: from common clock binding: handle hardware IP needed clocks, the
16 number of clocks may depend of the SoC type.
17 See ../clocks/clock-bindings.txt for details.
18 - clock-names: names of the clocks listed in clocks property in the same
33 - clocks: from common clock binding: handle hardware IP needed clocks, the
34 number of clocks may depend of the SoC type.
35 See ../clocks/clock-bindings.txt for details.
36 - clock-names: names of the clocks listed in clocks property in the same
66 - clocks: from common clock binding: handle hardware IP needed clocks, the
67 number of clocks may depend of the SoC type.
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/
Dst,stih4xx.txt15 - clocks: from common clock binding: handle hardware IP needed clocks, the
16 number of clocks may depend of the SoC type.
17 See ../clocks/clock-bindings.txt for details.
18 - clock-names: names of the clocks listed in clocks property in the same
33 - clocks: from common clock binding: handle hardware IP needed clocks, the
34 number of clocks may depend of the SoC type.
35 See ../clocks/clock-bindings.txt for details.
36 - clock-names: names of the clocks listed in clocks property in the same
66 - clocks: from common clock binding: handle hardware IP needed clocks, the
67 number of clocks may depend of the SoC type.
[all …]
/kernel/linux/linux-4.19/drivers/clk/bcm/
Dclk-bcm281xx.c27 .clocks = CLOCKS("ref_crystal"),
43 .clocks = CLOCKS("bbl_32k",
52 .clocks = CLOCKS("ref_crystal",
61 .clocks = CLOCKS("var_312m",
85 .clocks = CLOCKS("ref_crystal",
104 .clocks = CLOCKS("ref_crystal",
116 .clocks = CLOCKS("ref_crystal",
128 .clocks = CLOCKS("ref_crystal",
140 .clocks = CLOCKS("ref_crystal",
152 .clocks = CLOCKS("ref_crystal",
[all …]
/kernel/linux/linux-5.10/drivers/clk/bcm/
Dclk-bcm281xx.c27 .clocks = CLOCKS("ref_crystal"),
43 .clocks = CLOCKS("bbl_32k",
52 .clocks = CLOCKS("ref_crystal",
61 .clocks = CLOCKS("var_312m",
85 .clocks = CLOCKS("ref_crystal",
104 .clocks = CLOCKS("ref_crystal",
116 .clocks = CLOCKS("ref_crystal",
128 .clocks = CLOCKS("ref_crystal",
140 .clocks = CLOCKS("ref_crystal",
152 .clocks = CLOCKS("ref_crystal",
[all …]

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