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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/phy/
Dbrcm,stingray-usb-phy.txt1 Broadcom Stingray USB PHY
4 - compatible : should be one of the listed compatibles
5 - "brcm,sr-usb-combo-phy" is combo PHY has two PHYs, one SS and one HS.
6 - "brcm,sr-usb-hs-phy" is a single HS PHY.
7 - reg: offset and length of the PHY blocks registers
8 - #phy-cells:
9 - Must be 1 for brcm,sr-usb-combo-phy as it expects one argument to indicate
10 the PHY number of two PHYs. 0 for HS PHY and 1 for SS PHY.
11 - Must be 0 for brcm,sr-usb-hs-phy.
13 Refer to phy/phy-bindings.txt for the generic PHY binding properties
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Dintel,combo-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/intel,combo-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dilip Kota <eswara.kota@linux.intel.com>
14 controllers. A single Combophy provides two PHY instances.
18 pattern: "combophy(@.*|-[0-9a-f])*$"
22 - const: intel,combophy-lgm
23 - const: intel,combo-phy
30 - description: ComboPhy core registers
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Damlogic,meson-g12a-usb3-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/phy/amlogic,meson-g12a-usb3-pcie-phy.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Amlogic G12A USB3 + PCIE Combo PHY
11 - Neil Armstrong <narmstrong@baylibre.com>
16 - amlogic,meson-g12a-usb3-pcie-phy
24 clock-names:
26 - const: ref_clk
31 reset-names:
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Dcalxeda-combophy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/calxeda-combophy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 not by a dedicated PHY driver.
18 - Andre Przywara <andre.przywara@arm.com>
22 const: calxeda,hb-combophy
24 '#phy-cells':
36 - compatible
37 - reg
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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
Dintel_combo_phy.c1 // SPDX-License-Identifier: MIT
14 for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \
41 * CNL has just one set of registers, while gen11 has a set for each combo PHY.
42 * The CNL registers are equivalent to the gen11 PHY A registers, that's why we
46 cnl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy) in cnl_get_procmon_ref_values() argument
51 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy)); in cnl_get_procmon_ref_values()
77 enum phy phy) in cnl_set_procmon_ref_values() argument
82 procmon = cnl_get_procmon_ref_values(dev_priv, phy); in cnl_set_procmon_ref_values()
84 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW1(phy)); in cnl_set_procmon_ref_values()
86 val |= procmon->dw1; in cnl_set_procmon_ref_values()
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Dintel_dpll_mgr.h2 * Copyright © 2012-2016 Intel Corporation
38 __a > __b ? (__a - __b) : (__b - __a); })
49 * enum intel_dpll_id - possible DPLL ids
55 * @DPLL_ID_PRIVATE: non-shared dpll in use
57 DPLL_ID_PRIVATE = -1,
114 * @DPLL_ID_ICL_DPLL0: ICL/TGL combo PHY DPLL0
118 * @DPLL_ID_ICL_DPLL1: ICL/TGL combo PHY DPLL1
122 * @DPLL_ID_EHL_DPLL4: EHL combo PHY DPLL4
216 * struct intel_shared_dpll_state - hold the DPLL atomic state
239 * struct intel_shared_dpll_funcs - platform specific hooks for managing DPLLs
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/kernel/linux/linux-4.19/Documentation/devicetree/bindings/usb/
Dhisilicon,histb-xhci.txt6 - compatible: should be "hisilicon,hi3798cv200-xhci"
7 - reg: specifies physical base address and size of the registers
8 - interrupts : interrupt used by the controller
9 - clocks: a list of phandle + clock-specifier pairs, one for each
10 entry in clock-names
11 - clock-names: must contain
16 - resets: a list of phandle and reset specifier pairs as listed in
17 reset-names property.
18 - reset-names: must contain
20 - phys: a list of phandle + phy specifier pairs
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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/
Dhisilicon,histb-xhci.txt6 - compatible: should be "hisilicon,hi3798cv200-xhci"
7 - reg: specifies physical base address and size of the registers
8 - interrupts : interrupt used by the controller
9 - clocks: a list of phandle + clock-specifier pairs, one for each
10 entry in clock-names
11 - clock-names: must contain
16 - resets: a list of phandle and reset specifier pairs as listed in
17 reset-names property.
18 - reset-names: must contain
20 - phys: a list of phandle + phy specifier pairs
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/kernel/linux/linux-5.10/drivers/phy/amlogic/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Amlogic platforms
6 tristate "Meson8, Meson8b, Meson8m2 and GXBB USB2 PHY driver"
19 tristate "Meson GXL and GXM USB2 PHY drivers"
31 tristate "Meson G12A USB2 PHY driver"
42 tristate "Meson G12A USB3+PCIE Combo PHY driver"
48 Enable this to support the Meson USB3 + PCIE Combo PHY found
53 tristate "Meson AXG PCIE PHY driver"
59 Enable this to support the Meson MIPI + PCIE PHY found
64 tristate "Meson AXG MIPI + PCIE analog PHY driver"
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Dphy-meson-g12a-usb3-pcie.c1 // SPDX-License-Identifier: GPL-2.0
3 * Amlogic G12A USB3 + PCIE Combo PHY driver
15 #include <linux/phy/phy.h>
19 #include <dt-bindings/phy/phy.h>
60 struct phy *phy; member
79 regmap_write(priv->regmap, PHY_R4, reg); in phy_g12a_usb3_pcie_cr_bus_addr()
80 regmap_write(priv->regmap, PHY_R4, reg); in phy_g12a_usb3_pcie_cr_bus_addr()
82 regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_CAP_ADDR); in phy_g12a_usb3_pcie_cr_bus_addr()
84 ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val, in phy_g12a_usb3_pcie_cr_bus_addr()
90 regmap_write(priv->regmap, PHY_R4, reg); in phy_g12a_usb3_pcie_cr_bus_addr()
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/kernel/linux/linux-5.10/arch/arm64/boot/dts/broadcom/stingray/
Dstingray-usb.dtsi1 // SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause)
6 compatible = "simple-bus";
7 #address-cells = <2>;
8 #size-cells = <2>;
13 * to 40-bit
15 dma-ranges = <0 0 0 0 0x100 0x0>;
17 usbphy0: usb-phy@0 {
18 compatible = "brcm,sr-usb-combo-phy";
20 #phy-cells = <1>;
25 compatible = "generic-xhci";
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Dbcm958742k.dts4 * Copyright(c) 2016-2017 Broadcom. All rights reserved.
33 /dts-v1/;
35 #include "bcm958742-base.dtsi"
39 model = "Stingray Combo SVK (BCM958742K)";
43 enet-phy-lane-swap;
47 mmc-ddr-1_8v;
59 pinctrl-0 = <&spi0_pins>;
60 pinctrl-names = "default";
61 cs-gpios = <&gpio_hsls 34 0>;
64 spi-flash@0 {
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/kernel/linux/linux-4.19/Documentation/devicetree/bindings/phy/
Dcalxeda-combophy.txt4 - compatible : Should be "calxeda,hb-combophy"
5 - #phy-cells: Should be 1.
6 - reg : Address and size for Combination Phy registers.
7 - phydev: device ID for programming the combophy.
11 combophy5: combo-phy@fff5d000 {
12 compatible = "calxeda,hb-combophy";
13 #phy-cells = <1>;
/kernel/linux/linux-5.10/drivers/phy/intel/
Dphy-intel-lgm-combo.c1 // SPDX-License-Identifier: GPL-2.0
3 * Intel Combo-PHY driver
5 * Copyright (C) 2019-2020 Intel Corporation.
15 #include <linux/phy/phy.h>
20 #include <dt-bindings/phy/phy.h>
37 #define COMBO_PHY_ID(x) ((x)->parent->id)
38 #define PHY_ID(x) ((x)->id)
80 struct phy *phy; member
107 struct intel_combo_phy *cbphy = iphy->parent; in intel_cbphy_iphy_enable()
108 u32 mask = BIT(cbphy->phy_mode * 2 + iphy->id); in intel_cbphy_iphy_enable()
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PHY_INTEL_KEEMBAY_EMMC) += phy-intel-keembay-emmc.o
3 obj-$(CONFIG_PHY_INTEL_LGM_COMBO) += phy-intel-lgm-combo.o
4 obj-$(CONFIG_PHY_INTEL_LGM_EMMC) += phy-intel-lgm-emmc.o
/kernel/linux/linux-5.10/drivers/phy/allwinner/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Allwinner platforms
6 tristate "Allwinner sunxi SoC USB PHY driver"
19 This driver controls the entire USB PHY block, both the USB OTG
23 tristate "Allwinner A31 MIPI D-PHY Support"
32 MIPI-DSI support. If M is selected, the module will be
36 tristate "Allwinner sun9i SoC USB PHY driver"
47 This driver controls each individual USB 2 host PHY.
50 tristate "Allwinner H6 SoC USB3 PHY driver"
56 Enable this to support the USB3.0-capable transceiver that is
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/kernel/linux/linux-5.10/arch/arm/boot/dts/
Decx-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
20 #address-cells = <1>;
21 #size-cells = <1>;
22 compatible = "simple-bus";
23 interrupt-parent = <&intc>;
26 compatible = "calxeda,hb-ahci";
29 dma-coherent;
30 calxeda,port-phys = < &combophy5 0>, <&combophy0 0>,
33 calxeda,sgpio-gpio =<&gpioh 5 1>, <&gpioh 6 1>,
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Domap3-overo-base.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
18 compatible = "pwm-leds";
23 max-brightness = <127>;
24 linux,default-trigger = "mmc0";
29 compatible = "ti,omap-twl4030";
37 compatible = "regulator-fixed";
38 regulator-name = "hsusb2_vbus";
39 regulator-min-microvolt = <5000000>;
40 regulator-max-microvolt = <5000000>;
42 startup-delay-us = <70000>;
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/kernel/linux/linux-4.19/arch/arm/boot/dts/
Decx-common.dtsi2 * Copyright 2011-2012 Calxeda, Inc.
31 #address-cells = <1>;
32 #size-cells = <1>;
33 compatible = "simple-bus";
34 interrupt-parent = <&intc>;
37 compatible = "calxeda,hb-ahci";
40 dma-coherent;
41 calxeda,port-phys = <&combophy5 0 &combophy0 0
44 calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>;
45 calxeda,led-order = <4 0 1 2 3>;
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/kernel/linux/linux-4.19/drivers/gpu/drm/i915/
Dintel_dpll_mgr.h2 * Copyright © 2012-2016 Intel Corporation
33 __a > __b ? (__a - __b) : (__b - __a); })
44 * enum intel_dpll_id - possible DPLL ids
50 * @DPLL_ID_PRIVATE: non-shared dpll in use
52 DPLL_ID_PRIVATE = -1,
109 * @DPLL_ID_ICL_DPLL0: ICL combo PHY DPLL0
113 * @DPLL_ID_ICL_DPLL1: ICL combo PHY DPLL1
188 * struct intel_shared_dpll_state - hold the DPLL atomic state
211 * struct intel_shared_dpll_funcs - platform specific hooks for managing DPLLs
256 * struct dpll_info - display PLL platform specific info
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/kernel/linux/linux-5.10/drivers/phy/broadcom/
Dphy-bcm-sr-usb.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Broadcom
11 #include <linux/phy/phy.h>
25 /* USB PHY registers */
88 struct phy *phy; member
127 void __iomem *regs = phy_cfg->regs; in bcm_usb_ss_phy_init()
131 offset = phy_cfg->offset; in bcm_usb_ss_phy_init()
158 void __iomem *regs = phy_cfg->regs; in bcm_usb_hs_phy_init()
161 offset = phy_cfg->offset; in bcm_usb_hs_phy_init()
174 static int bcm_usb_phy_reset(struct phy *phy) in bcm_usb_phy_reset() argument
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/kernel/linux/linux-5.10/drivers/net/phy/
Dbcm-cygnus.c1 // SPDX-License-Identifier: GPL-2.0
7 #include "bcm-phy-lib.h"
11 #include <linux/phy.h>
17 /* Broadcom Cygnus Phy specific registers */
97 /* Apply AFE settings for the PHY */ in bcm_cygnus_config_init()
117 /* Re-initialize the PHY to apply AFE work-arounds and in bcm_cygnus_resume()
133 rev = phydev->phy_id & ~phydev->drv->phy_id_mask; in bcm_omega_config_init()
135 pr_info_once("%s: %s PHY revision: 0x%02x\n", in bcm_omega_config_init()
136 phydev_name(phydev), phydev->drv->name, rev); in bcm_omega_config_init()
172 /* Re-apply workarounds coming out suspend/resume */ in bcm_omega_resume()
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/kernel/linux/linux-4.19/arch/arm64/boot/dts/broadcom/stingray/
Dbcm958742k.dts4 * Copyright(c) 2016-2017 Broadcom. All rights reserved.
33 /dts-v1/;
35 #include "bcm958742-base.dtsi"
39 model = "Stingray Combo SVK (BCM958742K)";
43 enet-phy-lane-swap;
47 mmc-ddr-1_8v;
59 pinctrl-0 = <&spi0_pins>;
60 pinctrl-names = "default";
61 cs-gpios = <&gpio_hsls 34 0>;
64 spi-flash@0 {
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/include/
Dgrph_object_id.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
98 CLOCK_SOURCE_ID_EXTERNAL, /* ID (Phy) ref. clk. for DP */
102 /* Used to distinguish between programming pixel clock and ID (Phy) clock */
105 CLOCK_SOURCE_COMBO_PHY_PLL0, /*combo PHY PLL defines (DC 11.2 and up)*/
186 ENGINE_ID_VCE, /* wireless display pseudo-encoder */
190 ENGINE_ID_UNKNOWN = (-1L)
/kernel/linux/linux-4.19/drivers/gpu/drm/amd/display/include/
Dgrph_object_id.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
98 CLOCK_SOURCE_ID_EXTERNAL, /* ID (Phy) ref. clk. for DP */
102 /* Used to distinguish between programming pixel clock and ID (Phy) clock */
105 CLOCK_SOURCE_COMBO_PHY_PLL0, /*combo PHY PLL defines (DC 11.2 and up)*/
186 ENGINE_ID_VCE, /* wireless display pseudo-encoder */
190 ENGINE_ID_UNKNOWN = (-1L)

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