| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | armada-38x.dtsi | 56 clocks = <&coreclk 0>;
66 clocks = <&coreclk 0>;
76 clocks = <&coreclk 0>;
86 clocks = <&coreclk 0>;
96 clocks = <&coreclk 0>;
131 clocks = <&coreclk 2>;
138 clocks = <&coreclk 2>;
156 clocks = <&coreclk 0>;
166 clocks = <&coreclk 0>;
176 clocks = <&coreclk 0>;
[all …]
|
| D | armada-370-xp.dtsi | 56 clocks = <&coreclk 0>;
66 clocks = <&coreclk 0>;
76 clocks = <&coreclk 0>;
86 clocks = <&coreclk 0>;
96 clocks = <&coreclk 0>;
117 clocks = <&coreclk 0>;
126 clocks = <&coreclk 0>;
136 clocks = <&coreclk 0>;
146 clocks = <&coreclk 0>;
282 clocks = <&coreclk 0>;
[all …]
|
| D | armada-39x.dtsi | 93 clocks = <&coreclk 2>;
111 clocks = <&coreclk 0>;
121 clocks = <&coreclk 0>;
131 clocks = <&coreclk 0>;
141 clocks = <&coreclk 0>;
151 clocks = <&coreclk 0>;
161 clocks = <&coreclk 0>;
171 clocks = <&coreclk 0>;
181 clocks = <&coreclk 0>;
252 clocks = <&coreclk 0>;
[all …]
|
| D | armada-375.dtsi | 89 clocks = <&coreclk 0>;
99 clocks = <&coreclk 0>;
109 clocks = <&coreclk 0>;
119 clocks = <&coreclk 0>;
129 clocks = <&coreclk 0>;
159 clocks = <&coreclk 2>;
217 clocks = <&coreclk 0>;
229 clocks = <&coreclk 0>;
239 clocks = <&coreclk 0>;
249 clocks = <&coreclk 0>;
[all …]
|
| D | armada-370.dtsi | 116 clocks = <&coreclk 0>;
131 clocks = <&coreclk 0>;
155 clocks = <&coreclk 0>;
159 coreclk: mvebu-sar@18230 { label
293 clocks = <&coreclk 2>;
298 clocks = <&coreclk 2>;
302 clocks = <&coreclk 0>;
306 clocks = <&coreclk 0>;
|
| D | armada-xp.dtsi | 61 clocks = <&coreclk 0>;
73 clocks = <&coreclk 0>;
85 clocks = <&coreclk 0>;
89 coreclk: mvebu-sar@18230 { label
106 clocks = <&coreclk 1>;
255 clocks = <&coreclk 2>, <&refclk>;
261 clocks = <&coreclk 2>, <&refclk>;
|
| D | armada-xp-98dx3236.dtsi | 144 clocks = <&coreclk 0>;
152 clocks = <&coreclk 1>;
224 coreclk: mvebu-sar@f8204 { label
279 clocks = <&coreclk 2>, <&refclk>;
285 clocks = <&coreclk 2>, <&refclk>;
|
| /kernel/linux/linux-4.19/arch/arm/boot/dts/ |
| D | armada-38x.dtsi | 54 clocks = <&coreclk 0>;
64 clocks = <&coreclk 0>;
74 clocks = <&coreclk 0>;
84 clocks = <&coreclk 0>;
94 clocks = <&coreclk 0>;
124 clocks = <&coreclk 2>;
131 clocks = <&coreclk 2>;
150 clocks = <&coreclk 0>;
161 clocks = <&coreclk 0>;
171 clocks = <&coreclk 0>;
[all …]
|
| D | armada-370-xp.dtsi | 56 clocks = <&coreclk 0>;
66 clocks = <&coreclk 0>;
76 clocks = <&coreclk 0>;
86 clocks = <&coreclk 0>;
96 clocks = <&coreclk 0>;
118 clocks = <&coreclk 0>;
128 clocks = <&coreclk 0>;
138 clocks = <&coreclk 0>;
148 clocks = <&coreclk 0>;
284 clocks = <&coreclk 0>;
[all …]
|
| D | armada-39x.dtsi | 92 clocks = <&coreclk 2>;
111 clocks = <&coreclk 0>;
122 clocks = <&coreclk 0>;
133 clocks = <&coreclk 0>;
144 clocks = <&coreclk 0>;
154 clocks = <&coreclk 0>;
164 clocks = <&coreclk 0>;
174 clocks = <&coreclk 0>;
184 clocks = <&coreclk 0>;
255 clocks = <&coreclk 0>;
[all …]
|
| D | armada-375.dtsi | 89 clocks = <&coreclk 0>;
99 clocks = <&coreclk 0>;
109 clocks = <&coreclk 0>;
119 clocks = <&coreclk 0>;
129 clocks = <&coreclk 0>;
159 clocks = <&coreclk 2>;
217 clocks = <&coreclk 0>;
229 clocks = <&coreclk 0>;
240 clocks = <&coreclk 0>;
251 clocks = <&coreclk 0>;
[all …]
|
| D | armada-370.dtsi | 116 clocks = <&coreclk 0>;
131 clocks = <&coreclk 0>;
155 clocks = <&coreclk 0>;
159 coreclk: mvebu-sar@18230 { label
293 clocks = <&coreclk 2>;
298 clocks = <&coreclk 2>;
302 clocks = <&coreclk 0>;
306 clocks = <&coreclk 0>;
|
| D | armada-xp.dtsi | 61 clocks = <&coreclk 0>;
73 clocks = <&coreclk 0>;
85 clocks = <&coreclk 0>;
89 coreclk: mvebu-sar@18230 { label
106 clocks = <&coreclk 1>;
255 clocks = <&coreclk 2>, <&refclk>;
261 clocks = <&coreclk 2>, <&refclk>;
|
| D | armada-xp-98dx3236.dtsi | 144 clocks = <&coreclk 0>;
152 clocks = <&coreclk 1>;
224 coreclk: mvebu-sar@f8204 { label
284 clocks = <&coreclk 2>, <&refclk>;
290 clocks = <&coreclk 2>, <&refclk>;
|
| /kernel/linux/linux-4.19/drivers/soc/xilinx/ |
| D | xlnx_vcu.c | 103 * @coreclk: core clock frequency
111 u32 coreclk; member
296 u32 refclk, coreclk, mcuclk, inte, deci; in xvcu_set_vcu_pll_info() local
305 coreclk = xvcu_read(xvcu->logicore_reg_ba, VCU_CORE_CLK) * MHZ; in xvcu_set_vcu_pll_info()
307 if (!mcuclk || !coreclk) { in xvcu_set_vcu_pll_info()
314 dev_dbg(xvcu->dev, "Core clock from logicoreIP is %uHz\n", coreclk); in xvcu_set_vcu_pll_info()
351 mod = pll_clk % coreclk; in xvcu_set_vcu_pll_info()
353 divisor_core = pll_clk / coreclk; in xvcu_set_vcu_pll_info()
354 } else if (coreclk - mod < LIMIT) { in xvcu_set_vcu_pll_info()
355 divisor_core = pll_clk / coreclk; in xvcu_set_vcu_pll_info()
[all …]
|
| /kernel/linux/linux-5.10/drivers/soc/xilinx/ |
| D | xlnx_vcu.c | 103 * @coreclk: core clock frequency
111 u32 coreclk; member
296 u32 refclk, coreclk, mcuclk, inte, deci; in xvcu_set_vcu_pll_info() local
305 coreclk = xvcu_read(xvcu->logicore_reg_ba, VCU_CORE_CLK) * MHZ; in xvcu_set_vcu_pll_info()
307 if (!mcuclk || !coreclk) { in xvcu_set_vcu_pll_info()
314 dev_dbg(xvcu->dev, "Core clock from logicoreIP is %uHz\n", coreclk); in xvcu_set_vcu_pll_info()
351 mod = pll_clk % coreclk; in xvcu_set_vcu_pll_info()
353 divisor_core = pll_clk / coreclk; in xvcu_set_vcu_pll_info()
354 } else if (coreclk - mod < LIMIT) { in xvcu_set_vcu_pll_info()
355 divisor_core = pll_clk / coreclk; in xvcu_set_vcu_pll_info()
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/timer/ |
| D | marvell,armada-370-xp-timer.txt | 33 clocks = <&coreclk 2>;
42 clocks = <&coreclk 2>, <&refclk>;
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/timer/ |
| D | marvell,armada-370-xp-timer.txt | 33 clocks = <&coreclk 2>;
42 clocks = <&coreclk 2>, <&refclk>;
|
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/clock/ |
| D | qoriq-clock.txt | 60 A second input clock, called "coreclk", may be provided if
63 - clock-names: Required if a coreclk is present. Valid names are
64 "sysclk" and "coreclk".
82 5 coreclk must be 0
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/clock/ |
| D | qoriq-clock.txt | 67 A second input clock, called "coreclk", may be provided if
70 - clock-names: Required if a coreclk is present. Valid names are
71 "sysclk" and "coreclk".
89 5 coreclk must be 0
|
| /kernel/linux/linux-4.19/sound/soc/fsl/ |
| D | fsl_esai.c | 30 * @coreclk: clock source to access register
50 struct clk *coreclk; member
475 ret = clk_prepare_enable(esai_priv->coreclk); in fsl_esai_startup()
516 clk_disable_unprepare(esai_priv->coreclk); in fsl_esai_startup()
583 clk_disable_unprepare(esai_priv->coreclk); in fsl_esai_shutdown()
845 esai_priv->coreclk = devm_clk_get(&pdev->dev, "core"); in fsl_esai_probe()
846 if (IS_ERR(esai_priv->coreclk)) { in fsl_esai_probe()
848 PTR_ERR(esai_priv->coreclk)); in fsl_esai_probe()
849 return PTR_ERR(esai_priv->coreclk); in fsl_esai_probe()
|
| /kernel/linux/linux-5.10/drivers/clk/sifive/ |
| D | fu540-prci.c | 335 * __prci_coreclksel_use_hfclk() - switch the CORECLK mux to output HFCLK
336 * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
338 * Switch the CORECLK mux to the HFCLK input source; return once complete.
355 * __prci_coreclksel_use_corepll() - switch the CORECLK mux to output COREPLL
356 * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
358 * Switch the CORECLK mux to the PLL output clock; return once complete.
|
| /kernel/linux/linux-4.19/arch/arm64/boot/dts/freescale/ |
| D | fsl-ls1012a.dtsi | 65 coreclk: coreclk { label
69 clock-output-names = "coreclk";
271 clocks = <&sysclk &coreclk>;
272 clock-names = "sysclk", "coreclk";
|
| /kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/ |
| D | fsl-ls1012a.dtsi | 67 coreclk: coreclk { label
71 clock-output-names = "coreclk";
287 clocks = <&sysclk &coreclk>;
288 clock-names = "sysclk", "coreclk";
|
| /kernel/linux/linux-5.10/sound/soc/fsl/ |
| D | fsl_esai.c | 40 * @coreclk: clock source to access register
66 struct clk *coreclk; member
991 esai_priv->coreclk = devm_clk_get(&pdev->dev, "core"); in fsl_esai_probe()
992 if (IS_ERR(esai_priv->coreclk)) { in fsl_esai_probe()
994 PTR_ERR(esai_priv->coreclk)); in fsl_esai_probe()
995 return PTR_ERR(esai_priv->coreclk); in fsl_esai_probe()
1116 ret = clk_prepare_enable(esai->coreclk); in fsl_esai_runtime_resume()
1153 clk_disable_unprepare(esai->coreclk); in fsl_esai_runtime_resume()
1170 clk_disable_unprepare(esai->coreclk); in fsl_esai_runtime_suspend()
|