Searched +full:cortex +full:- +full:a57 (Results 1 – 25 of 86) sorted by relevance
1234
| /kernel/linux/linux-4.19/Documentation/devicetree/bindings/arm/ |
| D | cpus.txt | 13 with updates for 32-bit and 64-bit ARM systems provided in this document.
22 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
33 - cpus node
41 - #address-cells
52 # On 32-bit ARM 11 MPcore, ARM v7 or later systems
55 # On ARM v8 64-bit systems value should be set to 2,
58 in the system, #address-cells can be set to 1, since
61 - #size-cells
66 - cpu node
72 - device_type
[all …]
|
| D | topology.txt | 6 1 - Introduction
12 - cluster
13 - core
14 - thread
20 symmetric multi-threading (SMT) is supported or not.
43 2 - cpu-map node
46 The ARM CPU topology is defined within the cpu-map node, which is a direct
50 - cpu-map node
52 Usage: Optional - On ARM SMP systems provide CPUs topology to the OS.
55 cpu-map node.
[all …]
|
| D | idle-states.txt | 6 1 - Introduction
10 where cores can be put in different low-power states (ranging from simple
12 the range of dynamic idle states that a processor can enter at run-time, can be
19 - Running
20 - Idle_standby
21 - Idle_retention
22 - Sleep
23 - Off
29 wake-up capabilities, hence it is not considered in this document).
39 2 - idle-states definitions
[all …]
|
| D | pmu.txt | 5 representation in the device tree should be done as under:-
9 - compatible : should be one of
10 "apm,potenza-pmu"
11 "arm,armv8-pmuv3"
12 "arm,cortex-a73-pmu"
13 "arm,cortex-a72-pmu"
14 "arm,cortex-a57-pmu"
15 "arm,cortex-a53-pmu"
16 "arm,cortex-a35-pmu"
17 "arm,cortex-a17-pmu"
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/arm/ |
| D | cpus.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
71 * If cpus node's #address-cells property is set to 2
79 * If cpus node's #address-cells property is set to 1
[all …]
|
| D | idle-states.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
14 1 - Introduction
18 where cores can be put in different low-power states (ranging from simple wfi
20 range of dynamic idle states that a processor can enter at run-time, can be
27 - Running
28 - Idle_standby
[all …]
|
| /kernel/linux/linux-5.10/arch/arm64/boot/dts/hisilicon/ |
| D | hip05.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip05-d02";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
|
| D | hip06.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 compatible = "hisilicon,hip06-d03";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "arm,psci-0.2";
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
[all …]
|
| /kernel/linux/linux-4.19/arch/arm64/boot/dts/hisilicon/ |
| D | hip05.dtsi | 12 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 compatible = "hisilicon,hip05-d02";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 compatible = "arm,psci-0.2";
26 #address-cells = <1>;
27 #size-cells = <0>;
29 cpu-map {
90 compatible = "arm,cortex-a57", "arm,armv8";
[all …]
|
| D | hip06.dtsi | 12 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 compatible = "hisilicon,hip06-d03";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 compatible = "arm,psci-0.2";
26 #address-cells = <1>;
27 #size-cells = <0>;
29 cpu-map {
90 compatible = "arm,cortex-a57", "arm,armv8";
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/cpu/ |
| D | cpu-topology.txt | 6 1 - Introduction
12 - socket
13 - cluster
14 - core
15 - thread
18 symmetric multi-threading (SMT) is supported or not.
29 Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be
39 2 - cpu-map node
42 The ARM/RISC-V CPU topology is defined within the cpu-map node, which is a direct
46 - cpu-map node
[all …]
|
| /kernel/linux/linux-4.19/arch/arm64/boot/dts/freescale/ |
| D | fsl-ls2080a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
5 * Copyright 2014-2016 Freescale Semiconductor, Inc.
12 #include "fsl-ls208xa.dtsi"
17 compatible = "arm,cortex-a57";
20 cpu-idle-states = <&CPU_PW20>;
21 next-level-cache = <&cluster0_l2>;
22 #cooling-cells = <2>;
27 compatible = "arm,cortex-a57";
30 cpu-idle-states = <&CPU_PW20>;
[all …]
|
| /kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/ |
| D | fsl-ls2080a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
5 * Copyright 2014-2016 Freescale Semiconductor, Inc.
12 #include "fsl-ls208xa.dtsi"
17 compatible = "arm,cortex-a57";
20 cpu-idle-states = <&CPU_PW20>;
21 next-level-cache = <&cluster0_l2>;
22 #cooling-cells = <2>;
27 compatible = "arm,cortex-a57";
30 cpu-idle-states = <&CPU_PW20>;
[all …]
|
| /kernel/linux/linux-5.10/Documentation/translations/zh_CN/arm64/ |
| D | silicon-errata.txt | 1 Chinese translated version of Documentation/arm64/silicon-errata.rst
12 ---------------------------------------------------------------------
13 Documentation/arm64/silicon-errata.rst 的中文翻译
26 ---------------------------------------------------------------------
51 相应的内核配置（Kconfig）选项被加在 “内核特性（Kernel Features）”->
62 +----------------+-----------------+-----------------+-------------------------+
63 | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
64 | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
65 | ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
66 | ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 |
[all …]
|
| /kernel/linux/linux-4.19/Documentation/translations/zh_CN/arm64/ |
| D | silicon-errata.txt | 1 Chinese translated version of Documentation/arm64/silicon-errata.txt
12 ---------------------------------------------------------------------
13 Documentation/arm64/silicon-errata.txt 的中文翻译
26 ---------------------------------------------------------------------
51 相应的内核配置（Kconfig）选项被加在 “内核特性（Kernel Features）”->
62 +----------------+-----------------+-----------------+-------------------------+
63 | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
64 | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
65 | ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
66 | ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 |
[all …]
|
| /kernel/linux/linux-5.10/tools/perf/pmu-events/arch/arm64/ |
| D | mapfile.csv | 10 # to tools/perf/pmu-events/arch/arm64/.
14 #Family-model,Version,Filename,EventType
15 0x00000000410fd030,v1,arm/cortex-a53,core
16 0x00000000420f1000,v1,arm/cortex-a53,core
17 0x00000000410fd070,v1,arm/cortex-a57-a72,core
18 0x00000000410fd080,v1,arm/cortex-a57-a72,core
19 0x00000000410fd0b0,v1,arm/cortex-a76-n1,core
20 0x00000000410fd0c0,v1,arm/cortex-a76-n1,core
|
| /kernel/linux/linux-4.19/Documentation/arm64/ |
| D | silicon-errata.txt | 8 so-called "errata", which can cause it to deviate from the architecture
28 cases (e.g. those cases that both require a non-secure workaround *and*
33 Features" -> "ARM errata workarounds via the alternatives framework".
35 CPU is detected. For less-intrusive workarounds, a Kconfig option is not
46 +----------------+-----------------+-----------------+-----------------------------+
49 | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
50 | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
51 | ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
52 | ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 |
53 | ARM | Cortex-A53 | #845719 | ARM64_ERRATUM_845719 |
[all …]
|
| /kernel/linux/linux-5.10/arch/arm64/boot/dts/arm/ |
| D | juno.dts | 4 * Copyright (c) 2013-2014 ARM Ltd.
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
26 stdout-path = "serial0:115200n8";
30 compatible = "arm,psci-0.2";
35 #address-cells = <2>;
[all …]
|
| D | juno-r1.dts | 9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
13 #include "juno-cs-r1r2.dtsi"
17 compatible = "arm,juno-r1", "arm,juno", "arm,vexpress";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
27 stdout-path = "serial0:115200n8";
31 compatible = "arm,psci-0.2";
[all …]
|
| /kernel/linux/linux-4.19/arch/arm64/boot/dts/arm/ |
| D | juno-r1.dts | 9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
13 #include "juno-cs-r1r2.dtsi"
17 compatible = "arm,juno-r1", "arm,juno", "arm,vexpress";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
27 stdout-path = "serial0:115200n8";
31 compatible = "arm,psci-0.2";
[all …]
|
| D | juno.dts | 4 * Copyright (c) 2013-2014 ARM Ltd.
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
26 stdout-path = "serial0:115200n8";
30 compatible = "arm,psci-0.2";
35 #address-cells = <2>;
[all …]
|
| /kernel/linux/linux-4.19/drivers/soc/tegra/ |
| D | Kconfig | 3 # 32-bit ARM SoCs
60 # 64-bit ARM SoCs
72 Tegra124's "4+1" Cortex-A15 CPU complex.
81 the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53
84 and providing 256 CUDA cores. It supports hardware-accelerated en-
101 combination of Denver and Cortex-A57 CPU cores and a GPU based on
102 the Pascal architecture. It contains an ADSP with a Cortex-A9 CPU
104 multi-format support, ISP for image capture processing and BPMP for
|
| /kernel/linux/linux-5.10/drivers/soc/tegra/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
4 # 32-bit ARM SoCs
63 # 64-bit ARM SoCs
75 Tegra124's "4+1" Cortex-A15 CPU complex.
85 the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53
88 and providing 256 CUDA cores. It supports hardware-accelerated en-
105 combination of Denver and Cortex-A57 CPU cores and a GPU based on
106 the Pascal architecture. It contains an ADSP with a Cortex-A9 CPU
108 multi-format support, ISP for image capture processing and BPMP for
|
| /kernel/linux/linux-5.10/arch/arm64/boot/dts/amazon/ |
| D | alpine-v2.dtsi | 4 * Antoine Tenart <antoine.tenart@free-electrons.com>
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
35 /dts-v1/;
37 #include <dt-bindings/interrupt-controller/arm-gic.h>
41 compatible = "al,alpine-v2";
42 #address-cells = <2>;
43 #size-cells = <2>;
46 #address-cells = <2>;
47 #size-cells = <0>;
[all …]
|
| /kernel/linux/linux-4.19/arch/arm64/boot/dts/al/ |
| D | alpine-v2.dtsi | 4 * Antoine Tenart <antoine.tenart@free-electrons.com>
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
35 /dts-v1/;
37 #include <dt-bindings/interrupt-controller/arm-gic.h>
41 compatible = "al,alpine-v2";
42 #address-cells = <2>;
43 #size-cells = <2>;
46 #address-cells = <2>;
47 #size-cells = <0>;
[all …]
|
1234